This patch adds emulation for the mrs instruction. It is very incomplete
though and will need major rework to become as dynamic and good as the
cp15 handling.
Signed-off-by: Alexander Graf <ag...@suse.de>
---
target-arm/translate-a64.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index d5cc199..4879073 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1650,6 +1650,37 @@ static void handle_svc(DisasContext *s, uint32_t insn)
s->is_jmp = DISAS_SWI;
}
+static void handle_mrs(DisasContext *s, uint32_t insn)
+{
+ int dest = get_reg(insn);
+ int op2 = get_bits(insn, 5, 3);
+ int crm = get_bits(insn, 8, 4);
+ int crn = get_bits(insn, 12, 4);
+ int op1 = get_bits(insn, 16, 3);
+ int op0 = get_bits(insn, 19, 2);
+
+ /* XXX handle properly */
+ if (op0 == 3 && op1 == 3 && op2 == 2 && !crm && crn == 13) {
+ tcg_gen_ld_i64(cpu_reg(dest), cpu_env,
+ offsetof(CPUARMState, sr.tpidr_el0));
+ } else if (op0 == 3 && op1 == 3 && (op2 == 0 || op2 == 1) &&
+ crm == 4 && crn == 4) {
+ /* XXX this is probably wrong! */
+ tcg_gen_ld32u_i64(cpu_reg(dest), cpu_env,
+ offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
+ } else if (op0 == 3 && op1 == 3 && op2 == 1 && crm == 0 && crn == 0) {
+ /*
+ * CTR_EL0 [3:0] contains log2 of icache line size in words.
+ * CTR_EL0 [19:16] contains log2 of dcache line size in words.
+ */
+ tcg_gen_movi_i64(cpu_reg(dest), 0x30003);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "MRS: %d %d %d %d %d\n", op0, op1, op2, crm,
+ crn);
+ unallocated_encoding(s);
+ }
+}
+
void disas_a64_insn(CPUARMState *env, DisasContext *s)
{
uint32_t insn;
@@ -1778,6 +1809,8 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
case 0x15:
if (get_bits(insn, 29, 2) == 0x1) {
handle_cb(s, insn);
+ } else if (get_bits(insn, 20, 12) == 0xd53) {
+ handle_mrs(s, insn);
} else {
unallocated_encoding(s);
}
--
1.7.12.4
