From: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1 or not. i.e. it
was implementing a write-anything-to-clear strategy.
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id:
ed905b04d3343966ded425f06aa2224bc7a35b59.1386136219.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/net/cadence_gem.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 1619507..f2c734e 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1112,15 +1112,14 @@ static void gem_write(void *opaque, hwaddr offset,
uint64_t val,
/* Squash bits which are read only in write value */
val &= ~(s->regs_ro[offset]);
- /* Preserve (only) bits which are read only in register */
- readonly = s->regs[offset];
- readonly &= s->regs_ro[offset];
-
- /* Squash bits which are write 1 to clear */
- val &= ~(s->regs_w1c[offset] & val);
+ /* Preserve (only) bits which are read only and wtc in register */
+ readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
/* Copy register write to backing store */
- s->regs[offset] = val | readonly;
+ s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
+
+ /* do w1c */
+ s->regs[offset] &= ~(s->regs_w1c[offset] & val);
/* Handle register write side effects */
switch (offset) {
--
1.8.5
