On 12/11/2013 06:07 AM, Aurelien Jarno wrote:
> - tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
> + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_64);
MO_TEQ?
> - tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
> + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_32);
> opn = "sw";
> break;
> case OPC_SH:
> - tcg_gen_qemu_st16(t1, t0, ctx->mem_idx);
> + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_16);
> opn = "sh";
> break;
FWIW, I've been using the unsigned variants for stores, e.g. MO_TEUL.
> @@ -1869,7 +1869,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
> opc, int ft,
> {
> TCGv_i32 fp0 = tcg_temp_new_i32();
>
> - tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
> + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
> tcg_gen_trunc_tl_i32(fp0, t0);
> gen_store_fpr32(fp0, ft);
> tcg_temp_free_i32(fp0);
Since you've changed some of the extensions, notice that you can load directly
into fp0 now and avoid the truncates too.
r~
