Add support for the AArch32 floating-point VRINTZ instruction. Signed-off-by: Will Newton <will.new...@linaro.org> --- target-arm/translate.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c index 73e0e8d..153d0e6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3385,6 +3385,27 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpst); } break; + case 13: /* vrintz */ + if (dp) { + TCGv_ptr fpst = get_fpstatus_ptr(0); + TCGv_i32 tcg_rmode; + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(fpst); + } else { + TCGv_ptr fpst = get_fpstatus_ptr(0); + TCGv_i32 tcg_rmode; + tcg_rmode = tcg_const_i32(float_round_to_zero); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_rints(cpu_F0s, cpu_F0s, fpst); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + tcg_temp_free_ptr(fpst); + } + break; case 15: /* single<->double conversion */ if (dp) gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); -- 1.8.1.4