Here's the target-arm queue; nothing earthshaking here. I anticipate the queue will fill up with another 30+ patches within a week or so; please pull :-)
thanks -- PMM The following changes since commit 0169c511554cb0014a00290b0d3d26c31a49818f: Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2014-01-24 15:52:44 -0800) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140129 for you to fetch changes up to 984bc70fb5e6331cf3cbfa836373fefadf1435f9: arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes (2014-01-29 13:27:34 +0000) ---------------------------------------------------------------- target-arm queue: * implementation of first part of the A64 Neon instruction set * v8 AArch32 rounding and 16<->64 fp conversion instructions * add support for KVM ARM using the irqchip creation kernel API * fix MIDR value on Zynq boards * some minor bugfixes/code cleanups ---------------------------------------------------------------- Alex Bennée (5): target-arm: A64: Add SIMD ld/st multiple target-arm: A64: Add decode skeleton for SIMD data processing insns target-arm: A64: Add SIMD copy operations target-arm: A64: Add SIMD modified immediate group target-arm: A64: Add SIMD shift by immediate Alistair Francis (2): ARM: Convert MIDR to a property ZYNQ: Implement board MIDR control for Zynq Christoffer Dall (6): linux-headers: Update from Linus' master ba635f8 kvm: Introduce kvm_arch_irqchip_create kvm: Common device control API functions arm: vgic device control api support arm_gic: Introduce define for GIC_NR_SGIS arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes Michael Matz (3): target-arm: A64: Add SIMD TBL/TBLX target-arm: A64: Add SIMD ZIP/UZP/TRN target-arm: A64: Add SIMD across-lanes instructions Paolo Bonzini (1): display: avoid multi-statement macro Peter Maydell (11): target-arm: A64: Add SIMD ld/st single target-arm: A64: Add SIMD EXT target-arm: A64: Add SIMD scalar copy instructions hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting target-arm: A64: Add SIMD three-different multiply accumulate insns target-arm: A64: Add SIMD three-different ABDL instructions target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops target-arm: A64: Add top level decode for SIMD 3-same group target-arm: A64: Add logic ops from SIMD 3 same group target-arm: A64: Add integer ops from SIMD 3-same group target-arm: A64: Add simple SIMD 3-same floating point ops Will Newton (10): target-arm: Move arm_rmode_to_sf to a shared location. target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM target-arm: Add support for AArch32 FP VRINTR target-arm: Add support for AArch32 FP VRINTZ target-arm: Add support for AArch32 FP VRINTX target-arm: Add support for AArch32 SIMD VRINTX target-arm: Add set_neon_rmode helper target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM hw/arm/boot.c | 9 +- hw/arm/xilinx_zynq.c | 7 + hw/display/blizzard_template.h | 40 +- hw/display/pl110_template.h | 12 +- hw/display/pxa2xx_template.h | 22 +- hw/display/tc6393xb_template.h | 14 +- hw/intc/arm_gic.c | 21 +- hw/intc/arm_gic_kvm.c | 22 +- include/hw/intc/arm_gic_common.h | 2 + include/sysemu/kvm.h | 34 + kvm-all.c | 50 +- linux-headers/asm-arm/kvm.h | 28 + linux-headers/asm-arm64/kvm.h | 21 +- linux-headers/asm-x86/hyperv.h | 13 + linux-headers/linux/kvm.h | 2 + stubs/Makefile.objs | 1 + stubs/kvm.c | 7 + target-arm/cpu.c | 1 + target-arm/cpu.h | 2 + target-arm/helper-a64.c | 31 + target-arm/helper-a64.h | 1 + target-arm/helper.c | 45 + target-arm/helper.h | 1 + target-arm/kvm.c | 55 +- target-arm/kvm_arm.h | 17 +- target-arm/translate-a64.c | 2707 +++++++++++++++++++++++++++++++++++++- target-arm/translate.c | 251 ++++ trace-events | 1 + 28 files changed, 3325 insertions(+), 92 deletions(-) create mode 100644 stubs/kvm.c