On 3 February 2014 04:33, Chris Johns <chr...@rtems.org> wrote:
> If 1 is written to the SLCR's PSS_RESET_CTRL register request a qemu
> reset.
>
> The RTEMS BSPs use this bit and if -no-reboot is used qemu exits cleanly.
>
> Signed-off-by: Chris Johns <chr...@rtems.org>
> ---
> hw/misc/zynq_slcr.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
> index e42a5b0..f68a934 100644
> --- a/hw/misc/zynq_slcr.c
> +++ b/hw/misc/zynq_slcr.c
> @@ -394,7 +394,11 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
> case 0x1B0 ... 0x1D8:
> s->misc[(offset - 0x1B0) / 4] = val;
> break;
> - case 0x200 ... 0x25C:
> + case 0x200:
> + if (val == 1) {
> + qemu_system_reset_request();
> + }
Either missing "break" statement or missing "/* fall through */"
comment.
Is this really a "reset on specific value written" rather than
"bit 0 in the register is set to cause system reset"?
> + case 0x204 ... 0x25C:
> if (offset == 0x250) {
> goto bad_reg;
> }
thanks
-- PMM
