Am 14.02.2014 17:06, schrieb Sebastian Huber:
> The LEON3 processor has support for the CASA instruction which is
> normally only available for SPARC V9 processors. Binutils 2.24
> and GCC 4.9 will support this instruction for LEON3. GCC uses it to
> generate C11 atomic operations.
>
> The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
> not defined use a supervisor data load/store for an ASI of 0x80 in
> helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
> choosen according to the LEON3 documentation.
>
> The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
> Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
> access, Primary address space.
>
> Tested with the following program:
>
> #include <assert.h>
> #include <stdatomic.h>
>
> void test(void)
> {
> atomic_int a;
> int e;
> _Bool b;
>
> atomic_store(&a, 1);
> e = 1;
> b = atomic_compare_exchange_strong(&a, &e, 2);
> assert(b);
> assert(atomic_load(&a) == 2);
>
> atomic_store(&a, 3);
> e = 4;
> b = atomic_compare_exchange_strong(&a, &e, 5);
> assert(!b);
> assert(atomic_load(&a) == 3);
> }
>
> Tested also on a NGMP board with a LEON4 processor.
>
> v4: Fix coding style.
>
> Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
> Reviewed-by: Fabien Chouteau <chout...@adacore.com>
Reviewed-by: Andreas Färber <afaer...@suse.de>
but please put change logs below --- next time. No v5 needed for that,
committer can fix.
Also in my theory your Signed-off-by should be last when you submit a
patch, in particular when you apply changes on top of what a reviewer
has reviewed.
Thanks,
Andreas
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