On 10.02.2014, at 18:26, Tom Musta <tommu...@gmail.com> wrote: > This patch series adds the branch and integer instructions that were > introduced in Power ISA 2.07. Specifically, > > - There is a new conditional Branch to Address Register (bctar) instruction. > - The load/store quadword instructions are now supported in user mode (Book > I). > - Quadword atomic instructions have been added (lqarx, stqcx.). > > ISA 2.07 additions for other categories (VSX, Altivec, Decimal Floating Point, > transactional memory) are not included in this patch series; they will be > contributed via other patches. > > V2: Addressing review comments from Alex Graf: > (1) Refactored user-mode and Little Endian checks in the load and store > quadword instructions. > (2) Added reserve_val2 element to CPU state in support of quadword atomic > instructions. > > V3: Addressiew review comments from Alex Graf: > (1) Moved declaration of local variables to the beginning of the block (a > la > C89 standard). > (2) Fixed bugs in handling of secondary reservation doubleword used in > lqarx > and stqcx. instructions.
Thanks, applied to ppc-next. Alex
