From: Rob Herring <rob.herr...@linaro.org> Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts.
This problem is fixed by the 1st patch. The 2 other patches are problems I noticed while debugging this issue. They are more for correctness of the model than fixing any observed issues. Changes in v3: - Fix logic for checking if FIFO enable bit has changed - Add vmstate for UARTRSR register - Dropped patch 4 Rob Rob Herring (3): pl011: reset the fifo when enabled or disabled pl011: fix UARTRSR accesses corrupting the UARTCR value pl011: fix incorrect logic to set the RXFF flag hw/char/pl011.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 1.8.3.2
