On 10 June 2014 18:55, Fabian Aggeler <aggel...@ethz.ch> wrote:
> When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
> FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
> and a non-secure instance.
>
> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
> ---
> target-arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++++-----
> target-arm/helper.c | 27 +++++++++++++++++----------
> 2 files changed, 57 insertions(+), 15 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index c7d606e..13fa966 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -329,11 +329,46 @@ typedef struct CPUARMState {
> };
> uint64_t vbar_el2;
> uint64_t mvbar; /* (monitor) vector base address register */
> - uint32_t c13_fcse; /* FCSE PID. */
> - uint64_t contextidr_el1; /* Context ID. */
> - uint64_t tpidr_el0; /* User RW Thread register. */
> - uint64_t tpidrro_el0; /* User RO Thread register. */
> - uint64_t tpidr_el1; /* Privileged Thread register. */
> + struct { /* FCSE PID. */
> + uint32_t c13_fcseidr_ns;
> + uint32_t c13_fcseidr_s;
> + };
> + union { /* Context ID. */
> + struct {
> + uint64_t contextidr_ns;
> + uint64_t contextidr_s;
> + };
> + struct {
> + uint64_t contextidr_el1;
> + };
> + };
> + union { /* User RW Thread register. */
> + struct {
> + uint64_t tpidrurw_ns;
> + uint64_t tpidrurw_s;
> + };
> + struct {
> + uint64_t tpidr_el0;
> + };
> + };
> + union { /* User RO Thread register. */
> + struct {
> + uint64_t tpidruro_ns;
> + uint64_t tpidruro_s;
> + };
> + struct {
> + uint64_t tpidrro_el0;
> + };
> + };
> + union { /* Privileged Thread register. */
> + struct {
> + uint64_t tpidrprw_ns;
> + uint64_t tpidrprw_s;
> + };
> + struct {
> + uint64_t tpidr_el1;
> + };
> + };
> uint64_t c14_cntfrq; /* Counter Frequency register */
> uint64_t c14_cntkctl; /* Timer Control register */
> ARMGenericTimer c14_timer[NUM_GTIMERS];
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 2d085aa..aebcc62 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -396,12 +396,15 @@ static const ARMCPRegInfo cp_reginfo[] = {
> { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 =
> 0,
> .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2
> = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.c13_fcse),
> + .access = PL1_RW,
> + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.c13_fcseidr_s),
> + offsetof(CPUARMState, cp15.c13_fcseidr_ns) },
> .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
> { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
> .access = PL1_RW,
> - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
> + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.contextidr_s),
> + offsetof(CPUARMState, cp15.contextidr_ns) },
> .resetvalue = 0, .writefn = contextidr_write, .raw_writefn =
> raw_write, },
> REGINFO_SENTINEL
> };
> @@ -889,21 +892,25 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
> .access = PL0_RW,
> .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue =
> 0 },
> { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2
> = 2,
> - .access = PL0_RW,
> - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
> - .resetfn = arm_cp_reset_ignore },
> + .access = PL0_RW, .resetfn = arm_cp_reset_ignore,
> + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
> + offsetoflow32(CPUARMState, cp15.tpidrurw_ns)
> } },
> { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
> .access = PL0_R|PL1_W,
> .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue
> = 0 },
> { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2
> = 3,
> - .access = PL0_R|PL1_W,
> - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
> - .resetfn = arm_cp_reset_ignore },
> - { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
> + .access = PL0_R|PL1_W, .resetfn = arm_cp_reset_ignore,
> + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
> + offsetoflow32(CPUARMState, cp15.tpidruro_ns)
> } },
> + { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
> .access = PL1_RW,
> .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue =
> 0 },
> + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2
> = 4,
> + .access = PL1_RW, .resetfn = arm_cp_reset_ignore,
> + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
> + offsetoflow32(CPUARMState, cp15.tpidruro_ns)
> } },
>
Just discovered that TPIDRPRW is mapped to the wrong storage (tpidruro).
Should be mapped to tpidrprw.
> REGINFO_SENTINEL
> };
>
> @@ -4566,7 +4573,7 @@ static inline int get_phys_addr(CPUARMState *env,
> target_ulong address,
>
> /* Fast Context Switch Extension. */
> if (address < 0x02000000)
> - address += env->cp15.c13_fcse;
> + address += A32_BANKED_CURRENT_REG_GET(env, c13_fcseidr);
>
> if ((sctlr & SCTLR_M) == 0) {
> /* MMU/MPU disabled. */
> --
> 1.8.3.2
>
>
