On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
> ---
> target-ppc/translate.c | 23 +++++++++++------------
> 1 file changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 67f13f7..48c7b66 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -789,27 +789,26 @@ static void gen_cmpli(DisasContext *ctx)
> /* isel (PowerPC 2.03 specification) */
> static void gen_isel(DisasContext *ctx)
> {
> - int l1, l2;
> uint32_t bi = rC(ctx->opcode);
> uint32_t mask;
> TCGv_i32 t0;
> -
> - l1 = gen_new_label();
> - l2 = gen_new_label();
> + TCGv t1, true_op, zero;
>
> mask = 1 << (3 - (bi & 0x03));
> t0 = tcg_temp_new_i32();
This leaks t0 (never freed).
> tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
> - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
> + t1 = tcg_temp_new();
> + tcg_gen_extu_i32_tl(t1, t0);
> + zero = tcg_const_tl(0);
> if (rA(ctx->opcode) == 0)
> - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
> + true_op = zero;
> else
> - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
> - tcg_gen_br(l2);
> - gen_set_label(l1);
> - tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
> - gen_set_label(l2);
> - tcg_temp_free_i32(t0);
> + true_op = cpu_gpr[rA(ctx->opcode)];
> +
> + tcg_gen_movcond_tl(cpu_gpr[rD(ctx->opcode)], t1, zero,
> + true_op, cpu_gpr[rB(ctx->opcode)], TCG_COND_NE);
This doesnt compile for me ... the order of the arguments does not match what
is defined in tcg-op.h.
> + tcg_temp_free_i32(t1);
Just tcg_temp_free(t1);
> + tcg_temp_free(zero);
> }
>
> /* cmpb: PowerPC 2.05 specification */
>
