On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
> This will match the code we use in fpu_helper.c when we flip
> CRF_* bit-endianness.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
> ---
> target-ppc/translate.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 48c7b66..4ce7af4 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -794,7 +794,7 @@ static void gen_isel(DisasContext *ctx)
> TCGv_i32 t0;
> TCGv t1, true_op, zero;
>
> - mask = 1 << (3 - (bi & 0x03));
> + mask = 0x08 >> (bi & 0x03);
> t0 = tcg_temp_new_i32();
> tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
> t1 = tcg_temp_new();
> @@ -3870,7 +3870,7 @@ static inline void gen_bcond(DisasContext *ctx, int
> type)
> if ((bo & 0x10) == 0) {
> /* Test CR */
> uint32_t bi = BI(ctx->opcode);
> - uint32_t mask = 1 << (3 - (bi & 0x03));
> + uint32_t mask = 0x08 >> (bi & 0x03);
> TCGv_i32 temp = tcg_temp_new_i32();
>
> if (bo & 0x8) {
> @@ -3952,7 +3952,7 @@ static void glue(gen_, name)(DisasContext *ctx)
> else
> \
> tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);
> \
> tcg_op(t0, t0, t1);
> \
> - bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));
> \
> + bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);
> \
> tcg_gen_andi_i32(t0, t0, bitmask);
> \
> tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);
> \
> tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);
> \
>
Reviewed-by: Tom Musta <tommu...@gmail.com>
Tested-by: Tom Musta <tommu...@gmail.com>
