The signal is currently checked by 10 targets, but only actually raised by Sparc and ARM. For the sake of one test-and-branch, we can handle this generic bit generically.
Signed-off-by: Richard Henderson <r...@twiddle.net> --- cpu-exec.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index b977481..3913de0 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -404,17 +404,12 @@ int cpu_exec(CPUArchState *env) cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(cpu); } -#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ - defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ - defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || \ - defined(TARGET_UNICORE32) || defined(TARGET_TRICORE) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; cpu_loop_exit(cpu); } -#endif #if defined(TARGET_I386) if (interrupt_request & CPU_INTERRUPT_INIT) { cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); -- 1.9.3