On Fri, Sep 19, 2014 at 2:54 PM, Alistair Francis <alistai...@gmail.com> wrote:
> This patch adds the stm32f205 timers: TIM2, TIM3, TIM4 and TIM5
> to QEMU.
>
> Signed-off-by: Alistair Francis <alistai...@gmail.com>
> ---
> PUBLIC
> V2:
> - Reorder the Makefile config
> - Fix up the debug printing
> - Correct the timer event trigger
> Changes from RFC:
> - Small changes to functionality and style. Thanks to Peter C
> - Rename to make the timer more generic
> - Split the config settings to device level
>
> default-configs/arm-softmmu.mak | 1 +
> hw/timer/Makefile.objs | 2 +
> hw/timer/stm32f205_timer.c | 279
> +++++++++++++++++++++++++++++++++++++
> include/hw/timer/stm32f205_timer.h | 101 ++++++++++++++
> 4 files changed, 383 insertions(+)
> create mode 100644 hw/timer/stm32f205_timer.c
> create mode 100644 include/hw/timer/stm32f205_timer.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index f3513fa..cf23b24 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -78,6 +78,7 @@ CONFIG_NSERIES=y
> CONFIG_REALVIEW=y
> CONFIG_ZAURUS=y
> CONFIG_ZYNQ=y
> +CONFIG_STM32F205_TIMER=y
>
> CONFIG_VERSATILE_PCI=y
> CONFIG_VERSATILE_I2C=y
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index 2c86c3d..4bd9617 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -31,3 +31,5 @@ obj-$(CONFIG_DIGIC) += digic-timer.o
> obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
>
> obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
> +
> +common-obj-$(CONFIG_STM32F205_TIMER) += stm32f205_timer.o
> diff --git a/hw/timer/stm32f205_timer.c b/hw/timer/stm32f205_timer.c
> new file mode 100644
> index 0000000..37f2318
> --- /dev/null
> +++ b/hw/timer/stm32f205_timer.c
> @@ -0,0 +1,279 @@
> +/*
> + * STM32F205 Timer
> + *
> + * Copyright (c) 2014 Alistair Francis <alist...@alistair23.me>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/timer/stm32f205_timer.h"
> +
> +#ifndef STM_TIMER_ERR_DEBUG
> +#define STM_TIMER_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (STM_TIMER_ERR_DEBUG >= lvl) { \
> + qemu_log("stm32f205_timer: %s:" fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void stm32f205_timer_set_alarm(STM32f205TimerState *s);
> +
> +static void stm32f205_timer_interrupt(void *opaque)
> +{
> + STM32f205TimerState *s = opaque;
> +
> + DB_PRINT("Interrupt\n");
> +
> + if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
> + s->tim_sr |= 1;
> + qemu_irq_pulse(s->irq);
> + stm32f205_timer_set_alarm(s);
> + }
> +}
> +
> +static void stm32f205_timer_set_alarm(STM32f205TimerState *s)
> +{
> + uint32_t ticks;
> + int64_t now;
> +
> + DB_PRINT("Alarm raised at: 0x%x\n", s->tim_cr1);
"alarm set at". The callback would be the alarm raising.
> +
> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> + ticks = s->tim_arr - (s->tick_offset + (now * get_ticks_per_sec())) *
> + (s->tim_psc + 1);
Still doesn't add up just yet. You have:
ticks = s->tim_arr - ....
Implying ticks and s->tim_arr must be the same physical quantity which
must be timer ticks. However ...
> +
> + DB_PRINT("Alarm set in %d ticks\n", ticks);
> +
> + if (ticks == 0) {
> + timer_del(s->timer);
> + stm32f205_timer_interrupt(s);
> + } else {
> + timer_mod(s->timer, (now + (int64_t) ticks));
... you add ticks to now with is terms of ns, effectively adding
cycles and ns together. A frequency scaling factor is missing
somewhere.
> + DB_PRINT("Wait Time: %" PRId64 "\n", now + (int64_t) ticks);
> + }
> +}
> +
> +static void stm32f205_timer_reset(DeviceState *dev)
> +{
> + STM32f205TimerState *s = STM32F205TIMER(dev);
> +
> + s->tim_cr1 = 0;
> + s->tim_cr2 = 0;
> + s->tim_smcr = 0;
> + s->tim_dier = 0;
> + s->tim_sr = 0;
> + s->tim_egr = 0;
> + s->tim_ccmr1 = 0;
> + s->tim_ccmr2 = 0;
> + s->tim_ccer = 0;
> + s->tim_cnt = 0;
> + s->tim_psc = 0;
> + s->tim_arr = 0;
> + s->tim_ccr1 = 0;
> + s->tim_ccr2 = 0;
> + s->tim_ccr3 = 0;
> + s->tim_ccr4 = 0;
> + s->tim_dcr = 0;
> + s->tim_dmar = 0;
> + s->tim_or = 0;
> +}
> +
> +static uint64_t stm32f205_timer_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + STM32f205TimerState *s = opaque;
> +
> + DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
> +
> + switch (offset) {
> + case TIM_CR1:
> + return s->tim_cr1;
> + case TIM_CR2:
> + return s->tim_cr2;
> + case TIM_SMCR:
> + return s->tim_smcr;
> + case TIM_DIER:
> + return s->tim_dier;
> + case TIM_SR:
> + return s->tim_sr;
> + case TIM_EGR:
> + return s->tim_egr;
> + case TIM_CCMR1:
> + return s->tim_ccmr1;
> + case TIM_CCMR2:
> + return s->tim_ccmr2;
> + case TIM_CCER:
> + return s->tim_ccer;
> + case TIM_CNT:
> + s->tim_cnt = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
> /
> + get_ticks_per_sec());
> + return s->tim_cnt;
> + case TIM_PSC:
> + return s->tim_psc;
> + case TIM_ARR:
> + return s->tim_arr;
> + case TIM_CCR1:
> + return s->tim_ccr1;
> + case TIM_CCR2:
> + return s->tim_ccr2;
> + case TIM_CCR3:
> + return s->tim_ccr3;
> + case TIM_CCR4:
> + return s->tim_ccr4;
> + case TIM_DCR:
> + return s->tim_dcr;
> + case TIM_DMAR:
> + return s->tim_dmar;
> + case TIM_OR:
> + return s->tim_or;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "STM32F205_timer_write: Bad offset
> 0x%"HWADDR_PRIx"\n", offset);
> + }
> +
> + return 0;
> +}
> +
> +static void stm32f205_timer_write(void *opaque, hwaddr offset,
> + uint64_t val64, unsigned size)
> +{
> + STM32f205TimerState *s = opaque;
> + uint32_t value = val64;
> +
> + DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
> +
> + switch (offset) {
> + case TIM_CR1:
> + s->tim_cr1 = value;
> + return;
> + case TIM_CR2:
> + s->tim_cr2 = value;
> + return;
> + case TIM_SMCR:
> + s->tim_smcr = value;
> + return;
> + case TIM_DIER:
> + s->tim_dier = value;
> + return;
> + case TIM_SR:
> + /* This is set by hardware and cleared by software */
> + s->tim_sr &= value;
> + return;
> + case TIM_EGR:
> + s->tim_egr = value;
> + if (s->tim_egr & TIM_EGR_UG) {
> + /* Re-init the counter */
Do you just mean reset? Is this supposed to be a software reset?
> + stm32f205_timer_reset(DEVICE(s));
> + }
> + return;
> + case TIM_CCMR1:
> + s->tim_ccmr1 = value;
> + return;
> + case TIM_CCMR2:
> + s->tim_ccmr2 = value;
> + return;
> + case TIM_CCER:
> + s->tim_ccer = value;
> + return;
> + case TIM_CNT:
> + s->tim_cnt = value;
> + stm32f205_timer_set_alarm(s);
> + return;
> + case TIM_PSC:
> + s->tim_psc = value;
> + return;
> + case TIM_ARR:
> + s->tim_arr = value;
> + stm32f205_timer_set_alarm(s);
> + return;
> + case TIM_CCR1:
> + s->tim_ccr1 = value;
> + return;
> + case TIM_CCR2:
> + s->tim_ccr2 = value;
> + return;
> + case TIM_CCR3:
> + s->tim_ccr3 = value;
> + return;
> + case TIM_CCR4:
> + s->tim_ccr4 = value;
> + return;
> + case TIM_DCR:
> + s->tim_dcr = value;
> + return;
> + case TIM_DMAR:
> + s->tim_dmar = value;
> + return;
> + case TIM_OR:
> + s->tim_or = value;
> + return;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "STM32F205_timer_write: Bad offset
> 0x%"HWADDR_PRIx"\n", offset);
If you _ seperate words it should match the fn name exactly. You can
use plain english with:
STM32F205 timer write
or symbolic naming with:
stm32f205_timer_write
but my suggestion is the latter implemented with %s __func__.
> + }
> +}
> +
> +static const MemoryRegionOps stm32f205_timer_ops = {
> + .read = stm32f205_timer_read,
> + .write = stm32f205_timer_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void stm32f205_timer_init(Object *obj)
> +{
> + STM32f205TimerState *s = STM32F205TIMER(obj);
> + struct tm tm;
> +
tm is unused. It passes compile testing as it's address is take to a fn arg.
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
> +
> + memory_region_init_io(&s->iomem, obj, &stm32f205_timer_ops, s,
> + "stm32f205_timer", 0x2000);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
> +
> + qemu_get_timedate(&tm, 0);
> + s->tick_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
> get_ticks_per_sec();
> +
This is the only code that sets tick_offset. What's the exact semantic
you are looking for with tick_offset? The fact that this happens at
init only suggest that tick offset will always be 0 or trivially
small. Did you mean to do this in the reset? I can't see any offset
affecting code in reset and something probably should be there.
> + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f205_timer_interrupt,
> s);
> +}
> +
> +static void stm32f205_timer_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = stm32f205_timer_reset;
missing VMSD?
> +}
> +
> +static const TypeInfo stm32f205_timer_info = {
> + .name = TYPE_STM32F205_TIMER,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(STM32f205TimerState),
> + .instance_init = stm32f205_timer_init,
> + .class_init = stm32f205_timer_class_init,
> +};
> +
> +static void stm32f205_timer_register_types(void)
> +{
> + type_register_static(&stm32f205_timer_info);
> +}
> +
> +type_init(stm32f205_timer_register_types)
> diff --git a/include/hw/timer/stm32f205_timer.h
> b/include/hw/timer/stm32f205_timer.h
> new file mode 100644
> index 0000000..2686066
> --- /dev/null
> +++ b/include/hw/timer/stm32f205_timer.h
> @@ -0,0 +1,101 @@
> +/*
> + * STM32F205 Timer
> + *
> + * Copyright (c) 2014 Alistair Francis <alist...@alistair23.me>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_STM_TIMER_H
> +#define HW_STM_TIMER_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/timer.h"
> +#include "sysemu/sysemu.h"
> +
> +#define TIM_CR1 0x00
> +#define TIM_CR2 0x04
> +#define TIM_SMCR 0x08
> +#define TIM_DIER 0x0C
> +#define TIM_SR 0x10
> +#define TIM_EGR 0x14
> +#define TIM_CCMR1 0x18
> +#define TIM_CCMR2 0x1C
> +#define TIM_CCER 0x20
> +#define TIM_CNT 0x24
> +#define TIM_PSC 0x28
> +#define TIM_ARR 0x2C
> +#define TIM_CCR1 0x34
> +#define TIM_CCR2 0x38
> +#define TIM_CCR3 0x3C
> +#define TIM_CCR4 0x40
> +#define TIM_DCR 0x48
> +#define TIM_DMAR 0x4C
> +#define TIM_OR 0x50
> +
> +#define TIM_CR1_CEN 1
> +
> +#define TIM_EGR_UG 1
> +
> +#define TIM_CCER_CC2E (1 << 4)
> +#define TIM_CCMR1_OC2M2 (1 << 14)
> +#define TIM_CCMR1_OC2M1 (1 << 13)
> +#define TIM_CCMR1_OC2M0 (1 << 12)
> +#define TIM_CCMR1_OC2PE (1 << 11)
> +
> +#define TIM_DIER_UIE 1
> +
> +#define TYPE_STM32F205_TIMER "stm32f205-timer"
> +#define STM32F205TIMER(obj) OBJECT_CHECK(STM32f205TimerState, \
> + (obj), TYPE_STM32F205_TIMER)
> +
> +typedef struct STM32f205TimerState {
> + /* <private> */
> + SysBusDevice parent_obj;
> +
> + /* <public> */
> + MemoryRegion iomem;
> + QEMUTimer *timer;
> + qemu_irq irq;
> +
> + uint32_t tick_offset_vmstate;
copy_paste hangover.
Regards,
Peter
> + uint32_t tick_offset;
> +
> + uint32_t tim_cr1;
> + uint32_t tim_cr2;
> + uint32_t tim_smcr;
> + uint32_t tim_dier;
> + uint32_t tim_sr;
> + uint32_t tim_egr;
> + uint32_t tim_ccmr1;
> + uint32_t tim_ccmr2;
> + uint32_t tim_ccer;
> + uint32_t tim_cnt;
> + uint32_t tim_psc;
> + uint32_t tim_arr;
> + uint32_t tim_ccr1;
> + uint32_t tim_ccr2;
> + uint32_t tim_ccr3;
> + uint32_t tim_ccr4;
> + uint32_t tim_dcr;
> + uint32_t tim_dmar;
> + uint32_t tim_or;
> +} STM32f205TimerState;
> +
> +#endif
> --
> 1.9.1
>
>
