Hi,
On 14/07/14 10:55, Yongbok Kim wrote:
> +typedef struct CPUMIPSMSAContext CPUMIPSMSAContext;
> +struct CPUMIPSMSAContext {
> + int32_t msair;
> + int32_t msacsr;
> + int32_t msaaccess;
> + int32_t msasave;
> + int32_t msamodify;
> + int32_t msarequest;
> + int32_t msamap;
> + int32_t msaunmap;
> +
> + float_status fp_status;
> +};
> +
> typedef union fpr_t fpr_t;
> union fpr_t {
> float64 fd; /* ieee double precision */
> float32 fs[2];/* ieee single precision */
> uint64_t d; /* binary double fixed-point */
> uint32_t w[2]; /* binary single fixed-point */
> +/* FPU/MSA register mapping is not tested on big-endian hosts. */
> + wr_t wr; /* vector data */
> };
> /* define FP_ENDIAN_IDX to access the same location
> * in the fpr_t union regardless of the host endianness
> @@ -175,6 +237,7 @@ typedef struct CPUMIPSState CPUMIPSState;
> struct CPUMIPSState {
> TCState active_tc;
> CPUMIPSFPUContext active_fpu;
> + CPUMIPSMSAContext active_msa;
According to the manual, only the msair register is shared between
thread contexts, each thread context has its own version of the rest of
the msa registers, so most of this should be TCState I think.
Cheers
James
