On Thu, Jan 22, 2015 at 12:03:52AM -0800, sfel...@gmail.com wrote: > +SECTION 7: Switch Control > +========================= > + > +This section covers switch-wide register settings. > + > +Control > +------- > + > +This register is used for low level control of the switch. > + > + CONTROL: offset 0x0300, 32-bit, (W) > + > + bit name description > + ------------------------------------------------------------------------ > + [0] CONTROL_RESET If set, device will perform reset
This doesn't block the patch series, but I have a question: Reset is not defined. What exactly gets reset? How does the CPU detect that the device has completed the reset procedure? Is this supposed to be synchronous? If yes, is that a good idea (i.e. hopefully resetting doesn't involve any blocking operations or operations that take a long time)? Stefan
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