This set of patches implements handling for the MSI redirection hint
bit. The RH bit is used in logical destination mode to indicate that
the delivery of the interrupt shall only be to the lowest priority
candidate LAPIC.
Currently, there is no handling of the MSI RH bit. This patch implements
the following logic:
* DM=0, RH=* : Physical destination mode. Interrupt is delivered to
the LAPIC with the matching APIC ID. (Subject to
the usual restrictions, i.e. no broadcast dest)
* DM=1, RH=0 : Logical destination mode without redirection. Interrupt
is delivered to all LAPICs in the logical group
specified by the IRQ's destination map and delivery
mode.
* DM=1, RH=1 : Logical destination mode with redirection. Interrupt
is delivered only to the lowest priority LAPIC in the
logical group specified by the dest map and the
delivery mode. Delivery semantics are otherwise
specified by the delivery_mode of the IRQ, which
is unchanged.
These changes reflect those made in the KVM in
http://www.spinics.net/lists/kvm/msg114915.html ("kvm: x86: Implement
handling of RH=1 for MSI delivery in KVM"), which are under review but
are largely settled in terms of functionality.
James Sullivan (3):
apic: Added helper function apic_match_dest,
apic_match_[physical,logical]_dest
apic: Set and pass in RH bit for MSI interrupts
apic: Implement handling of RH=1 for MSI interrupt delivery
hw/intc/apic.c | 70 +++++++++++++++++++++++++++++++++++++-------------
hw/intc/ioapic.c | 2 +-
include/hw/i386/apic.h | 3 ++-
trace-events | 2 +-
4 files changed, 56 insertions(+), 21 deletions(-)
--
2.3.3
