Resend of <1427224426-9025-1-git-send-email-sullivan.jame...@gmail.com>,
correcting the labelling of one of the patches to correct sequential order.
Changes in v2:
* Merged in low priority IRQ delivery implementation to RH bit
handling implementation, since both rely on the same helper
functions for priority arbitration.
* Corrected use of MSI data register => addr register when setting
msi_redir_hint in apic_send_msi().
This set of patches adds the following features to QEMU:
* Low priority delivery arbitration. Currently the first present CPU
is always selected when lowpri delivery mode is used, and no
arbitration is performed. Implemented arbitration in
apic_bus_deliver() by adding the following functions:
1) apic_get_arb_pri(APICCommonState *s)
2) apic_compare_prio(APICCommonState *s1, APICCommonState *s2);
3) apic_lowest_prio(const uint32_t *deliver_bitmask)
* RH Bit handling for MSI messages. See below.
Currently, there is no handling of the MSI RH bit. This patch implements
the following logic:
* DM=0, RH=* : Physical destination mode. Interrupt is delivered to
the LAPIC with the matching APIC ID. (Subject to
the usual restrictions, i.e. no broadcast dest)
* DM=1, RH=0 : Logical destination mode without redirection. Interrupt
is delivered to all LAPICs in the logical group
specified by the IRQ's destination map and delivery
mode.
* DM=1, RH=1 : Logical destination mode with redirection. Interrupt
is delivered only to the lowest priority LAPIC in the
logical group specified by the dest map and the
delivery mode. Delivery semantics are otherwise
specified by the delivery_mode of the IRQ, which
is unchanged.
These changes reflect those made in the KVM in
http://www.spinics.net/lists/kvm/msg114915.html ("kvm: x86: Implement
handling of RH=1 for MSI delivery in KVM"), which have been reviewed and
discussed on the KVM mailing list.
James Sullivan (5):
apic: Implement LAPIC low priority arbitration functions
apic: Implement low priority arbitration for IRQ delivery
apic: Added helper function apic_match_dest,
apic_match_[physical,logical]_dest
apic: Set and pass in RH bit for MSI interrupts
apic: Implement handling of RH=1 for MSI interrupt delivery
hw/intc/apic.c | 137 ++++++++++++++++++++++++++++++++++++-------------
hw/intc/ioapic.c | 2 +-
include/hw/i386/apic.h | 3 +-
trace-events | 2 +-
4 files changed, 105 insertions(+), 39 deletions(-)
--
2.3.4
