From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Hi,
This is round 3 of our series towards support for EL2 for AArch64.
This series depends on Gregs exception target el infrastructure
patch series that is not yet upstream.
P0 - P2 are fixes without dependencies.
P3 is probably something that should be fixed in Gregs series.
P4 and on add a bunch of EL2 regs and timer features.
Comments welcome!
Best regards,
Edgar
Edgar E. Iglesias (18):
target-arm: Correct accessfn for CNTP_{CT}VAL_EL0
target-arm: Correct accessfn for CNTV_TVAL_EL0
target-arm: Remove unneeded '+'
target-arm: Route timer access traps to EL1
target-arm: Add MAIR_EL2
target-arm: Add TCR_EL2
target-arm: Add SCTLR_EL2
target-arm: Add TTBR0_EL2
target-arm: Add TLBI_ALLE1{IS}
target-arm: Add TLBIALLE2
target-arm: Add TPIDR_EL2
target-arm: Add TLBI_VAE2{IS}
target-arm: Add access to PAR_EL1
target-arm: Add CNTVOFF_EL2
target-arm: Add CNTHCTL_EL2
target-arm: Pass timeridx as argument to various timer functions
target-arm: Add HYP timer
hw/arm/virt: Connect the Hypervisor timer
hw/arm/virt.c | 3 +
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 2 +
target-arm/cpu.h | 5 +-
target-arm/helper.c | 309 +++++++++++++++++++++++++++++++++++++++++++++------
5 files changed, 288 insertions(+), 32 deletions(-)
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1.9.1
