On 27 May 2015 at 14:29, Yongbok Kim <yongbok....@imgtec.com> wrote:
> Add probe_write() in order to support such functionality that probes
> if a specified guest virtual address exists in TLB and is writable.
> The function forces a tlb_fill() if the address does not exist or is
> not writable, as a result an exception can occur.
>
> Signed-off-by: Yongbok Kim <yongbok....@imgtec.com>
> ---
> include/exec/exec-all.h | 2 ++
> softmmu_template.h | 18 ++++++++++++++++++
> 2 files changed, 20 insertions(+), 0 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index b58cd47..af51203 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -109,6 +109,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
> vaddr,
> hwaddr paddr, MemTxAttrs attrs,
> int prot, int mmu_idx, target_ulong size);
> void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
> +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
> + uintptr_t retaddr);
> #else
> static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> diff --git a/softmmu_template.h b/softmmu_template.h
> index 9cb1659..1558b8b 100644
> --- a/softmmu_template.h
> +++ b/softmmu_template.h
> @@ -548,6 +548,24 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState
> *env, target_ulong addr,
> helper_te_st_name(env, addr, val, oi, GETRA());
> }
>
> +#if DATA_SIZE == 1
> +/* Probe if the specified guest virtual address exists in TLB and is
> writable,
> + if not force a tlb_fill(). As a result an exception can occur. */
/* Probe for whether the specified guest write access is permitted.
* If it is not permitted then an exception will be taken in the same
* way as if this were a real write access (and we will not return).
* Otherwise the function will return, and there will be a valid
* entry in the TLB for this access.
*/
> +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
> + uintptr_t retaddr)
> +{
> + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> +
> + if ((addr & TARGET_PAGE_MASK)
> + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> + /* TLB entry is for a different page */
> + if (!VICTIM_TLB_HIT(addr_write)) {
> + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx,
> retaddr);
> + }
> + }
> +}
> +#endif
> #endif /* !defined(SOFTMMU_CODE_ACCESS) */
>
> #undef READ_ACCESS_TYPE
> --
-- PMM
