On Mon, Jun 1, 2015 at 11:44 AM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 1 June 2015 at 19:04, Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> wrote:
>> Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
>> and both thumb and ARM div instructions.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
>
> This patch needs to go last, not first -- implement all
> the support the R5 needs, and only then let somebody
> create one.
>
OK
> -- PMM
>
>> ---
>> target-arm/cpu.c | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> index 4a888ab..4872d9c 100644
>> --- a/target-arm/cpu.c
>> +++ b/target-arm/cpu.c
>> @@ -794,6 +794,32 @@ static void arm_v7m_class_init(ObjectClass *oc, void
>> *data)
>> cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
>> }
>>
>> +static void cortex_r5_initfn(Object *obj)
>> +{
>> + ARMCPU *cpu = ARM_CPU(obj);
>> +
>> + set_feature(&cpu->env, ARM_FEATURE_V7);
>> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
>
> Should we have a feature bit for "this is an R profile
> core" ? For instance THUMB_DIV is mandatory for v7R
> and so we could infer it in cpu realize.
>
So is this best done as rename of ARM_FEATURE_MPU? We can still set R
profile for ARMv5 MPU capable procs in much the same way we do with
"EL2" and "EL3" for preV8.
Regards,
Peter
>> + set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
>> + set_feature(&cpu->env, ARM_FEATURE_V7MP);
>
> This will turn on a bunch of TLB invalidate insns we don't want
> (v7mp_cp_reginfo assumes VMSA).
>
> It also won't give the right value for MPIDR; see the comment
> in mpidr_read():
> /* Cores which are uniprocessor (non-coherent)
> * but still implement the MP extensions set
> * bit 30. (For instance, A9UP.) However we do
> * not currently model any of those cores.
> */
>
> The R5 (from r1p0 and up) is such a core...
>
>> + set_feature(&cpu->env, ARM_FEATURE_MPU);
>> + cpu->midr = 0x411fc153; /* r1p3 */
>> + cpu->id_pfr0 = 0x0131;
>> + cpu->id_pfr1 = 0x001;
>> + cpu->id_dfr0 = 0x010400;
>> + cpu->id_afr0 = 0x0;
>> + cpu->id_mmfr0 = 0x0210030;
>> + cpu->id_mmfr1 = 0x00000000;
>> + cpu->id_mmfr2 = 0x01200000;
>> + cpu->id_mmfr3 = 0x0211;
>> + cpu->id_isar0 = 0x2101111;
>> + cpu->id_isar1 = 0x13112111;
>> + cpu->id_isar2 = 0x21232141;
>> + cpu->id_isar3 = 0x01112131;
>> + cpu->id_isar4 = 0x0010142;
>> + cpu->id_isar5 = 0x0;
>> +}
>> +
>> static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
>> { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2
>> = 0,
>> .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>> @@ -1185,6 +1211,7 @@ static const ARMCPUInfo arm_cpus[] = {
>> { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
>> { .name = "cortex-m3", .initfn = cortex_m3_initfn,
>> .class_init = arm_v7m_class_init },
>> + { .name = "cortex-r5", .initfn = cortex_r5_initfn },
>> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
>> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
>> { .name = "cortex-a15", .initfn = cortex_a15_initfn },
>> --
>> 2.4.2.3.g2ffcb72
>>
>
> thanks
> -- PMM
>
