On Tue, Jun 16, 2015 at 05:36:12PM -0700, Peter Crosthwaite wrote:
> Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
> and both thumb and ARM div instructions.
>
> Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
> don't have a lot of meaning in QEMU yet. Raz them so the guest can
> proceed if they are read. The TCM registers will return a size of 0,
> indicating no TCM.
>
> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> Based loosely on an old patch of Andreas' for the cortex-r4.
> changed since v1:
> Squashed in R5 specific CP regs patch
> Reordered to be after supporting patches
> set mp_is_up
>
> target-arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 4010d81..dce91bb 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -847,6 +847,43 @@ static void arm_v7m_class_init(ObjectClass *oc, void
> *data)
> cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
> }
>
> +static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
> + /* Dummy the TCM region regs for the moment */
> + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
> + .access = PL1_RW, .type = ARM_CP_CONST },
> + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
> + .access = PL1_RW, .type = ARM_CP_CONST },
> + REGINFO_SENTINEL
> +};
> +
> +static void cortex_r5_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + set_feature(&cpu->env, ARM_FEATURE_V7);
> + set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
> + set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
> + set_feature(&cpu->env, ARM_FEATURE_V7MP);
> + set_feature(&cpu->env, ARM_FEATURE_MPU);
> + cpu->midr = 0x411fc153; /* r1p3 */
> + cpu->id_pfr0 = 0x0131;
> + cpu->id_pfr1 = 0x001;
> + cpu->id_dfr0 = 0x010400;
> + cpu->id_afr0 = 0x0;
> + cpu->id_mmfr0 = 0x0210030;
> + cpu->id_mmfr1 = 0x00000000;
> + cpu->id_mmfr2 = 0x01200000;
> + cpu->id_mmfr3 = 0x0211;
> + cpu->id_isar0 = 0x2101111;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232141;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x0010142;
> + cpu->id_isar5 = 0x0;
> + cpu->mp_is_up = true;
> + define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
> +}
> +
> static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
> { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 =
> 0,
> .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -1238,6 +1275,7 @@ static const ARMCPUInfo arm_cpus[] = {
> { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
> { .name = "cortex-m3", .initfn = cortex_m3_initfn,
> .class_init = arm_v7m_class_init },
> + { .name = "cortex-r5", .initfn = cortex_r5_initfn },
> { .name = "cortex-a8", .initfn = cortex_a8_initfn },
> { .name = "cortex-a9", .initfn = cortex_a9_initfn },
> { .name = "cortex-a15", .initfn = cortex_a15_initfn },
> --
> 2.4.3.3.g905f831
>
