rt, rs were swapped
Signed-off-by: Yongbok Kim <[email protected]>
Reviewed-by: Aurelien Jarno <[email protected]>
Reviewed-by: Leon Alrae <[email protected]>
---
target-mips/translate.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1d128ee..97b74ba 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12991,12 +12991,12 @@ static void gen_pool32axf (CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
case RDPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
- gen_load_srsgpr(rt, rs);
+ gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
- gen_store_srsgpr(rt, rs);
+ gen_store_srsgpr(rs, rt);
break;
default:
goto pool32axf_invalid;
--
1.7.5.4
