target-arm queue before hardfreeze: these are pretty much all
bugfixes.
-- PMM
The following changes since commit f50a1640fb82708a5d528dee1ace42a224b95b15:
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into
staging (2015-07-05 20:35:47 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20150706
for you to fetch changes up to 257621a9566054472d1d55a819880d0f9da02bda:
arm_mptimer: Respect IT bit state (2015-07-06 10:26:35 +0100)
----------------------------------------------------------------
target-arm queue:
* TLBI ALLEI1IS should operate on all CPUs, not just this one
* Fix interval interrupt of cadence ttc in decrement mode
* Implement YIELD insn to yield in ARM and Thumb translators
* ARM GIC: reset all registers
* arm_mptimer: fix timer shutdown and mode change
* arm_mptimer: respect IT bit state
----------------------------------------------------------------
Dmitry Osipenko (2):
arm_mptimer: Fix timer shutdown and mode change
arm_mptimer: Respect IT bit state
Johannes Schlatow (1):
Fix interval interrupt of cadence ttc when timer is in decrement mode
Peter Maydell (3):
target-arm: Split DISAS_YIELD from DISAS_WFE
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
hw/intc/arm_gic_common.c: Reset all registers
Sergey Fedorov (1):
target-arm: fix write helper for TLBI ALLE1IS
hw/intc/arm_gic_common.c | 21 ++++++++++++++++++---
hw/timer/arm_mptimer.c | 13 ++++++++++---
hw/timer/cadence_ttc.c | 9 ++++-----
target-arm/helper.c | 2 +-
target-arm/helper.h | 1 +
target-arm/op_helper.c | 18 +++++++++++++++---
target-arm/translate-a64.c | 6 ++++++
target-arm/translate.c | 7 +++++++
target-arm/translate.h | 1 +
9 files changed, 63 insertions(+), 15 deletions(-)
