We managed to forget to implement the Secure physical timer when we added TZ support for AArch32. This patchset fixes the omission, and wires up its interrupt.
This patchset sits on top of https://git.linaro.org/people/peter.maydell/qemu-arm.git target-arm-post-2.4 which is where I'm putting patches which I've reviewed but which aren't 2.4 material. Currently that's just Edgar's hyp timer series. (Warning, branch will rebase.) Since we're now wiring up four timer interrupts in virt and a15mpcore, I switched them to a data-driven loop for neatness. Incidentally, the reason that kernels worked and continue to work even if they're booting Secure is that they cope with timer interrupts coming in via either the NS timer irq line or the S timer irq line. The next step is to put the secure-GIC patchset on top of this. I think we're going to need to make the virt board default to non-secure at that point, because the QEMU UEFI blob doesn't cope with being booted Secure. That's probably for the best anyway, since then it will be the same for TCG and KVM. thanks -- PMM Peter Maydell (4): target-arm: Add the AArch64 view of the Secure physical timer target-arm: Add AArch32 banked register access to secure physical timer hw/arm/virt: Wire up secure timer interrupt hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts hw/arm/virt.c | 28 +++++++------ hw/cpu/a15mpcore.c | 21 ++++++---- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 + target-arm/cpu.h | 3 +- target-arm/helper.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 148 insertions(+), 21 deletions(-) -- 1.9.1