Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net>
Reviewed-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com>
---
Changes since v1:
* not present on v1
Changes since v2:
* not present on v2
Changes since v3:
* not present on v3
Changes since v4:
* not present on v4
Changes since v5:
* not present on v5
Changes since v6:
* not present on v6
Changes since v7:
* not present on v7
Changes since v8:
* not present on v8
Changes since v9:
* Added 3 I2C devices to i.MX31 SOC
Changes since v10:
* no change.
Changes since v11:
* no change.
Changes since v12:
* no change.
Changes since v13:
* Spelling fix in comments
* Space cleanup
* Patch title fix.
Changes since v14:
* no change.
hw/arm/fsl-imx31.c | 30 ++++++++++++++++++++++++++++++
include/hw/arm/fsl-imx31.h | 11 +++++++++++
2 files changed, 41 insertions(+)
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index 1681ecf..87548c8 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -50,6 +50,11 @@ static void fsl_imx31_init(Object *obj)
object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
}
+
+ for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+ object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
+ qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
+ }
}
static void fsl_imx31_realize(DeviceState *dev, Error **errp)
@@ -154,6 +159,31 @@ static void fsl_imx31_realize(DeviceState *dev, Error
**errp)
epit_table[i].irq));
}
+ /* Initialize all I2C */
+ for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } i2c_table[FSL_IMX31_NUM_I2CS] = {
+ { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
+ { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
+ { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
+ };
+
+ /* Initialize the I2C */
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ /* Map I2C memory */
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
+ /* Connect I2C IRQ to PIC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ i2c_table[i].irq));
+ }
+
/* On a real system, the first 16k is a `secure boot rom' */
memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
"imx31.secure_rom",
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index 128006f..891166f 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -31,6 +31,7 @@
#define FSL_IMX31_NUM_UARTS 2
#define FSL_IMX31_NUM_EPITS 2
+#define FSL_IMX31_NUM_I2CS 3
typedef struct FslIMX31State {
/*< private >*/
@@ -43,6 +44,7 @@ typedef struct FslIMX31State {
IMXSerialState uart[FSL_IMX31_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX31_NUM_EPITS];
+ IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
MemoryRegion secure_rom;
MemoryRegion rom;
MemoryRegion iram;
@@ -57,10 +59,16 @@ typedef struct FslIMX31State {
#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
#define FSL_IMX31_IRAM_SIZE 0x4000
+#define FSL_IMX31_I2C1_ADDR 0x43F80000
+#define FSL_IMX31_I2C1_SIZE 0x4000
+#define FSL_IMX31_I2C3_ADDR 0x43F84000
+#define FSL_IMX31_I2C3_SIZE 0x4000
#define FSL_IMX31_UART1_ADDR 0x43F90000
#define FSL_IMX31_UART1_SIZE 0x4000
#define FSL_IMX31_UART2_ADDR 0x43F94000
#define FSL_IMX31_UART2_SIZE 0x4000
+#define FSL_IMX31_I2C2_ADDR 0x43F98000
+#define FSL_IMX31_I2C2_SIZE 0x4000
#define FSL_IMX31_CCM_ADDR 0x53F80000
#define FSL_IMX31_CCM_SIZE 0x4000
#define FSL_IMX31_GPT_ADDR 0x53F90000
@@ -95,5 +103,8 @@ typedef struct FslIMX31State {
#define FSL_IMX31_GPT_IRQ 29
#define FSL_IMX31_UART2_IRQ 32
#define FSL_IMX31_UART1_IRQ 45
+#define FSL_IMX31_I2C1_IRQ 10
+#define FSL_IMX31_I2C2_IRQ 4
+#define FSL_IMX31_I2C3_IRQ 3
#endif /* FSL_IMX31_H */
--
2.1.4
