On Friday, September 4, 2015, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 4 September 2015 at 07:49, Pavel Fedin <p.fe...@samsung.com > <javascript:;>> wrote: > > Hi! This message is mainly for Peter. I say you reviewed my major sets, > but looks like missed this > > one. If it is OK, we could apply it, and i could successfully bring back > the missing part in > > vGICv3-enabled hw/arm/virt.c which attaches irqchip to CPUs. This would > make us more ready for TCG > > version of GICv3. > > It's not clear to me that the TCG version of GICv3 > emulation should need to have such a link. The original > emulation patchset was definitely not handling the > GIC-to-CPU connection in the right way, and I haven't > seen anybody post an updated version of those patches > which fixes it. I'd rather not add this link until > we have the GIC emulation design sorted out and > we know that we need it. > > thanks > -- PMM > Hi, First I want to apologize for been absent for such a long time. As far as I remember Peter suggested that with the GICv3 support the routine define_arm_cp_regs_with_opaque should be used, where the "opaque" is the gic object. This "opaque" is later accessed from the register info "opaque" member. I assume the idea is to take hw/arm/pxa2xx.c as an example. I also assume that the code that registers the system instructions should be called from the GICv3 code as the GICv3 mode of operation determines if the access to the GICv3 is via memory access or via system registers. Am I right? I hope to release a new version soon. Best regards, S.P.
