I think I may have found the culprit - athlon is defined as 'PPRO_FEATURES + some additional features'.
If PPRO_FEATURES is what I think it is (pentium pro) why does it have SSE and SSE2 defined? It should end with MMX. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1469342 Title: qemu-i386 pentium3/athlon incorrect instruction set Status in QEMU: Won't Fix Bug description: Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 from 20150609 using the -cpu pentium3 switch results in flawless execution whereas it should crash with SIGILL as P3 only had SSE and not SSE2. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1469342/+subscriptions
