From: James Hogan <james.ho...@imgtec.com>
MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these
encodings to the MIPS disassembly table.
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Reviewed-by: Leon Alrae <leon.al...@imgtec.com>
Signed-off-by: James Hogan <james.ho...@imgtec.com>
Signed-off-by: Richard Henderson <r...@twiddle.net>
Message-Id: <1443788657-14537-3-git-send-email-james.ho...@imgtec.com>
---
disas/mips.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 01336a8..bf0bbaf 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2420,9 +2420,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"hibernate","", 0x42000023, 0xffffffff, 0,
0, V1 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,
0, I33 },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 },
+{"jr", "s", 0x00000009, 0xfc1fffff, UBD|RD_s, 0,
I32R6 }, /* jalr */
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0,
I32 },
+{"jr.hb", "s", 0x00000409, 0xfc1fffff, UBD|RD_s, 0,
I32R6 }, /* jalr.hb */
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0,
I1 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
--
2.4.3
