On 26 February 2016 at 20:07, dcb <1550...@bugs.launchpad.net> wrote: > Public bug reported: > > [qemu/target-arm/helper.c:5493]: (style) Expression '(X & 0x1f) != > 0xf80f0000' is always true. > > Source code is > > (env->uncached_cpsr & CPSR_M) != CPSR_USER && > > but > > ./qemu/target-arm/cpu.h:#define CPSR_M (0x1fU) > > ./qemu/target-arm/cpu.h:#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
Yeah, that's a bug. Should be ARM_CPU_MODE_USR, not CPSR_USER. thanks -- PMM
