Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
---
v2 -> v3:
- substitute f_get_excp_flags() with get_float_exception_flags()
- remove float32_squash_input_denormal()
target-tricore/fpu_helper.c | 26 ++++++++++++++++++++++++++
target-tricore/helper.h | 1 +
target-tricore/translate.c | 3 +++
3 files changed, 30 insertions(+)
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index f8d29b0..332d471 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -104,3 +104,29 @@ uint32_t helper_f##op(CPUTriCoreState *env, uint32_t r1,
uint32_t r2) \
}
FADD_SUB(add)
FADD_SUB(sub)
+
+uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
+{
+ uint32_t flags;
+ float32 arg1 = make_float32(r1);
+ float32 arg2 = make_float32(r2);
+ float32 f_result;
+
+ f_result = float32_mul(arg1, arg2, &env->fp_status);
+
+ flags = get_float_exception_flags(&env->fp_status);
+ if (flags) {
+ /* If the output is a NaN, but the inputs aren't,
+ we return a unique value. */
+ if ((flags & float_flag_invalid)
+ && !float32_is_any_nan(arg1)
+ && !float32_is_any_nan(arg2)) {
+ f_result = MUL_NAN;
+ }
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return (uint32_t)f_result;
+
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2f4a2bb..ac41190 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -107,6 +107,7 @@ DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32,
i32, i32)
DEF_HELPER_1(unpack, i64, i32)
DEF_HELPER_3(fadd, i32, env, i32, i32)
DEF_HELPER_3(fsub, i32, env, i32, i32)
+DEF_HELPER_3(fmul, i32, env, i32, i32)
/* dvinit */
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 3f54987..38ac8d6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6672,6 +6672,9 @@ static void decode_rr_divide(CPUTriCoreState *env,
DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_MUL_F:
+ gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
default:
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
--
2.7.2
