Hello,
This is a first mini-serie of patches adding support for new ppc SPRs.
They were taken from Ben's larger patchset adding the ppc powernv
platform and they should already be useful for the pseries guest
migration.
Initial patches come from :
https://github.com/ozbenh/qemu/commits/powernv
The changes are mostly due to the rebase on Dave's 2.6 branch:
https://github.com/dgibson/qemu/commits/ppc-for-2.6 ppc-for-2.6-20160316
A couple more are bisect and checkpatch fixes and finally some patches
were merge to reduce the noise.
Changes since v2:
- removed LPCR setting in patch 04/10 "ppc: Create cpu_ppc_set_papr() helper"
- fixed has_iamr condition in gen_spr_amr()
Changes since v1:
- dropped patches which are not fixes for 2.6 :
ppc: Add number of threads per core to the processor definition
ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
ppc: Better figure out if processor has HV mode
ppc: Add placeholder SPRs for DPDES and DHDES on P8
ppc: SPURR & PURR are HV writeable and privileged
ppc: Add dummy write to VTB
ppc: Add dummy POWER8 MPPR register
- fixed else if condition in gen_op_mfspr()
- removed all hunks except those related to AMOR and DAWR*
The patchset is also available here:
https://github.com/legoater/qemu/commits/for-2.6
It was quickly tested with a pseries guest using KVM and TCG.
Thanks,
C.
Benjamin Herrenschmidt (10):
ppc: Update SPR definitions
ppc: Add macros to register hypervisor mode SPRs
ppc: Add a bunch of hypervisor SPRs to Book3s
ppc: Create cpu_ppc_set_papr() helper
ppc: Add dummy SPR_IC for POWER8
ppc: Initialize AMOR in PAPR mode
ppc: Fix writing to AMR/UAMOR
ppc: Add POWER8 IAMR register
ppc: Add dummy CIABR SPR
ppc: A couple more dummy POWER8 Book4 regs
hw/ppc/spapr.c | 11 +-
target-ppc/cpu.h | 61 +++++++++--
target-ppc/translate.c | 26 +++--
target-ppc/translate_init.c | 241 ++++++++++++++++++++++++++++++++++++++++----
4 files changed, 291 insertions(+), 48 deletions(-)
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2.1.4
