No, nothing is lost. The plan is to add this functionality at a later time. ________________________________________ From: Maciej Rozycki Sent: Monday, April 25, 2016 7:06 AM To: Aleksandar Markovic Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org; pro...@gmail.com; kbast...@mail.uni-paderborn.de; mark.cave-ayl...@ilande.co.uk; ag...@suse.de; blauwir...@gmail.com; jcmvb...@gmail.com; Aleksandar Markovic; qemu-...@nongnu.org; qemu-...@nongnu.org; Petar Jovanovic; pbonz...@redhat.com; Miodrag Dinic; edgar.igles...@gmail.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de; Aurelien Jarno; r...@twiddle.net Subject: Re: [PATCH v5 5/9] target-mips: Activate IEEE 274-2008 signaling NaN bit meaning
On Mon, 18 Apr 2016, Aleksandar Markovic wrote: > Functions mips_cpu_reset() and msa_reset() are updated so that flag > snan_bit_is_one is properly set for any Mips FPU/MSA configuration. > For main FPUs, CPUs with FCR31's FCR31_NAN2008 bit set will invoke > set_snan_bit_is_one(0). For MSA, as it is IEEE 274-2008 compliant > from it inception, set_snan_bit_is_one(0) will always be invoked. I have skimmed over the series -- have you lost MIPSr3 support (writable FCSR ABS2008 and NAN2008 bits) in porting? Maciej
