On 2016-04-28 09:05, Peter Xu wrote: > This patch enables interrupt remapping for PCI devices. > > To play the trick, one memory region "iommu_ir" is added as child region > of the original iommu memory region, covering range 0xfeeXXXXX (which is > the address range for APIC). All the writes to this range will be taken > as MSI, and translation is carried out only when IR is enabled. > > Idea suggested by Paolo Bonzini.
This still lacks source (device ID) identification, right? Were did the memory write attribute thing go? Given that you actually introduce a separate MSI target address space for the IOAPIC (btw, once there will be more than one instance, like on real hw today) and that you will need yet another one for each HPET, why not address this with a common scheme now, ie. by transmitting the source ID along the write via that attribute? Jan
