From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi,
Another round of patches towards EL2 support. This one adds partial Instruction Syndrome generation for Data Aborts while running in AArch64. I don't feel very confident with the way I collect the regsize info used to fill out the SF field. Feedback on that would be great. Once we sort out the details on how this should be implemented we can fill out the parts needed for AArch32. Possibly in a future version of this same series. Comments welcome! Best regards, Edgar ChangeLog: v2 -> v3: * Commented on inst start extra words * Add macro for word2 shift * Move ISS field collection closer to tcg_gen_qemu_ld/st * Changed logic to compute regsize for disas_ld_lit * Introduce syn_data_abort_with_iss/no_iss * Rename some isv naming to iss * Drop the patch: "Use isyn.swstep.ex to hold the is_ldex state" v1 -> v2: * Reworked the syndrome generation code to reuse syn_data_abort for the encoding. * Reworded a bunch of comments. * Fixed thumb vs 16bit IL field issue. Edgar E. Iglesias (7): tcg: Add tcg_set_insn_param gen-icount: Use tcg_set_insn_param target-arm: Add the IL flag to syn_data_abort target-arm: Split data abort syndrome generator target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9 target-arm/translate-a64.c: Unify some of the ldst_reg decoding target-arm: A64: Create Instruction Syndromes for Data Aborts include/exec/gen-icount.h | 16 ++--- target-arm/cpu.h | 12 +++- target-arm/internals.h | 24 ++++++- target-arm/op_helper.c | 47 ++++++++++-- target-arm/translate-a64.c | 175 +++++++++++++++++++++++++++++++++++---------- target-arm/translate.c | 5 +- target-arm/translate.h | 2 + tcg/tcg.h | 6 ++ 8 files changed, 233 insertions(+), 54 deletions(-) -- 2.5.0
