These two patches are seperated from v6 series of Intel IOMMU IR support. Existing read-only bits of IOAPIC registers are writable. We'd better follow the spec to make it read-only. The first patch did this.
The 2nd patch emulated real IOAPIC behavior that remote IRR bits are cleared when configuring edge-triggered interrupts. This "feature" is used by Linux kernel to do explicit EOI for 0x1X IOAPICs. For more information, please refer to the comments in patch 2. This one depends on patch 1 to work. Peter Xu (2): ioapic: keep RO bits for IOAPIC entry ioapic: clear remote irr bit for edge-triggered interrupts hw/intc/ioapic.c | 33 +++++++++++++++++++++++++++++++++ include/hw/i386/ioapic_internal.h | 5 +++++ 2 files changed, 38 insertions(+) -- 2.4.11
