On Tue, 31 May 2016 20:48:38 +0300
Marcel Apfelbaum <mar...@redhat.com> wrote:
> Re-use the pci acpi hotplug code and enable it only for
> the new machines using the 'acpi-pci-hotplug-with-bridge-support'
> compat property.
>
> Signed-off-by: Marcel Apfelbaum <mar...@redhat.com>
> ---
> hw/acpi/ich9.c | 31 +++++++++++++++++++++++++++++++
> hw/isa/lpc_ich9.c | 12 ++++++++++++
> include/hw/acpi/ich9.h | 4 ++++
> include/hw/i386/pc.h | 7 ++++++-
> 4 files changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> index 27e978f..499f744 100644
> --- a/hw/acpi/ich9.c
> +++ b/hw/acpi/ich9.c
> @@ -230,6 +230,7 @@ static void pm_reset(void *opaque)
> }
> pm->smi_en_wmask = ~0;
>
> + acpi_pcihp_reset(&pm->acpi_pci_hotplug);
> acpi_update_sci(&pm->acpi_regs, pm->irq);
> }
>
> @@ -273,6 +274,10 @@ void ich9_pm_init(PCIDevice *lpc_pci,
> ICH9LPCPMRegs *pm, pm->powerdown_notifier.notify = pm_powerdown_req;
> qemu_register_powerdown_notifier(&pm->powerdown_notifier);
>
> + acpi_pcihp_init(OBJECT(lpc_pci), &pm->acpi_pci_hotplug,
> lpc_pci->bus,
> + pci_address_space_io(lpc_pci),
> + pm->use_acpi_pci_hotplug);
this will register IO window quite high for q35 at ACPI_PCIHP_ADDR
0xae00
maybe it should be different for q35 like with CPU hotplug,
for example below 0xcd8
> +
> acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci),
> OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE);
>
> @@ -306,6 +311,21 @@ static void
> ich9_pm_set_memory_hotplug_support(Object *obj, bool value,
> s->pm.acpi_memory_hotplug.is_enabled = value; }
>
> +static bool ich9_pm_get_acpi_pci_hotplug_support(Object *obj, Error
> **errp) +{
> + ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
> +
> + return s->pm.use_acpi_pci_hotplug;
> +}
> +
> +static void ich9_pm_set_acpi_pci_hotplug_support(Object *obj, bool
> value,
> + Error **errp)
> +{
> + ICH9LPCState *s = ICH9_LPC_DEVICE(obj);
> +
> + s->pm.use_acpi_pci_hotplug = value;
> +}
> +
> static void ich9_pm_get_disable_s3(Object *obj, Visitor *v, const
> char *name, void *opaque, Error **errp)
> {
> @@ -397,6 +417,7 @@ void ich9_pm_add_properties(Object *obj,
> ICH9LPCPMRegs *pm, Error **errp) {
> static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
> pm->acpi_memory_hotplug.is_enabled = true;
> + pm->use_acpi_pci_hotplug = true;
> pm->disable_s3 = 0;
> pm->disable_s4 = 0;
> pm->s4_val = 2;
> @@ -412,6 +433,10 @@ void ich9_pm_add_properties(Object *obj,
> ICH9LPCPMRegs *pm, Error **errp) ich9_pm_get_memory_hotplug_support,
> ich9_pm_set_memory_hotplug_support,
> NULL);
> + object_property_add_bool(obj,
> "acpi-pci-hotplug-with-bridge-support",
> + ich9_pm_get_acpi_pci_hotplug_support,
> + ich9_pm_set_acpi_pci_hotplug_support,
> + NULL);
> object_property_add(obj, ACPI_PM_PROP_S3_DISABLED, "uint8",
> ich9_pm_get_disable_s3,
> ich9_pm_set_disable_s3,
> @@ -436,6 +461,9 @@ void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm,
> DeviceState *dev, Error **errp) object_dynamic_cast(OBJECT(dev),
> TYPE_PC_DIMM)) { acpi_memory_plug_cb(&pm->acpi_regs, pm->irq,
> &pm->acpi_memory_hotplug, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
> + acpi_pcihp_device_plug_cb(&pm->acpi_regs, pm->irq,
> + &pm->acpi_pci_hotplug, dev, errp);
> } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
> acpi_cpu_plug_cb(&pm->acpi_regs, pm->irq, &pm->gpe_cpu, dev,
> errp); } else {
> @@ -451,6 +479,9 @@ void
> ich9_pm_device_unplug_request_cb(ICH9LPCPMRegs *pm, DeviceState *dev,
> object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))
> { acpi_memory_unplug_request_cb(&pm->acpi_regs, pm->irq,
> &pm->acpi_memory_hotplug, dev, errp);
> + } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
> + acpi_pcihp_device_unplug_cb(&pm->acpi_regs, pm->irq,
> + &pm->acpi_pci_hotplug, dev,
> errp); } else {
> error_setg(errp, "acpi: device unplug request for not
> supported device" " type: %s", object_get_typename(OBJECT(dev)));
> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
> index 4f8ca45..fb2ce08 100644
> --- a/hw/isa/lpc_ich9.c
> +++ b/hw/isa/lpc_ich9.c
> @@ -33,6 +33,7 @@
> #include "hw/hw.h"
> #include "qapi/visitor.h"
> #include "qemu/range.h"
> +#include "qapi/error.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> #include "hw/i386/pc.h"
> @@ -511,6 +512,15 @@ static const MemoryRegionOps rcrb_mmio_ops = {
> .endianness = DEVICE_LITTLE_ENDIAN,
> };
>
> +static void ich9_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
> +{
> + ICH9LPCState *s = opaque;
> +
> + if (!pci_bus_is_express(pci_bus)) {
> + qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s),
> &error_abort);
> + }
> +}
> +
> static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
> {
> ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
> @@ -534,6 +544,8 @@ static void ich9_lpc_machine_ready(Notifier *n,
> void *opaque) /* floppy */
> pci_conf[0x82] |= 0x08;
> }
> +
> + pci_for_each_bus(s->d.bus, ich9_update_bus_hotplug, s);
> }
>
> /* reset control */
> diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
> index 63fa198..c30c125 100644
> --- a/include/hw/acpi/ich9.h
> +++ b/include/hw/acpi/ich9.h
> @@ -22,6 +22,7 @@
> #define HW_ACPI_ICH9_H
>
> #include "hw/acpi/acpi.h"
> +#include "hw/acpi/pcihp.h"
> #include "hw/acpi/cpu_hotplug.h"
> #include "hw/acpi/memory_hotplug.h"
> #include "hw/acpi/acpi_dev_interface.h"
> @@ -52,6 +53,9 @@ typedef struct ICH9LPCPMRegs {
>
> MemHotplugState acpi_memory_hotplug;
>
> + AcpiPciHpState acpi_pci_hotplug;
> + bool use_acpi_pci_hotplug;
> +
> uint8_t disable_s3;
> uint8_t disable_s4;
> uint8_t s4_val;
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 9ca2309..ee941b1 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -357,7 +357,12 @@ int e820_get_num_entries(void);
> bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
>
> #define PC_COMPAT_2_5 \
> - HW_COMPAT_2_5
> + HW_COMPAT_2_5 \
should it be 2_6 by now?
> + {\
> + .driver = "ICH9-LPC",\
> + .property = "acpi-pci-hotplug-with-bridge-support",\
> + .value = "off",\
> + },
>
> /* Helper for setting model-id for CPU models that changed model-id
> * depending on QEMU versions up to QEMU 2.4.
