lxvb16x: Load VSX Vector Byte*16
lxvh8x: Load VSX Vector Halfword*8
Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com>
---
target-ppc/helper.h | 2 ++
target-ppc/mem_helper.c | 33 +++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 57 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 257bfca..2fe93ae 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -287,6 +287,8 @@ DEF_HELPER_2(mtvscr, void, env, avr)
DEF_HELPER_3(lvebx, void, env, avr, tl)
DEF_HELPER_3(lvehx, void, env, avr, tl)
DEF_HELPER_3(lvewx, void, env, avr, tl)
+DEF_HELPER_2(lxvb16x, i64, env, tl)
+DEF_HELPER_2(lxvh8x, i64, env, tl)
DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index bf6c44a..cf32f73 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -326,6 +326,39 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#define LXV(name, access, swap, type, elems) \
+uint64_t helper_##name(CPUPPCState *env, \
+ target_ulong addr) \
+{ \
+ type r[elems] = {0}; \
+ int i, index, bound, step; \
+ if (msr_le) { \
+ index = elems - 1; \
+ bound = -1; \
+ step = -1; \
+ } else { \
+ index = 0; \
+ bound = elems; \
+ step = 1; \
+ } \
+ \
+ for (i = index; i != bound; i += step) { \
+ if (needs_byteswap(env)) { \
+ r[i] = swap(access(env, addr, GETPC())); \
+ } else { \
+ r[i] = access(env, addr, GETPC()); \
+ } \
+ addr = addr_add(env, addr, sizeof(type)); \
+ } \
+ return *((uint64_t *)r); \
+}
+
+#define I(x) (x)
+LXV(lxvb16x, cpu_ldub_data_ra, I, uint8_t, 8)
+LXV(lxvh8x, cpu_lduw_data_ra, bswap16, uint16_t, 4)
+#undef I
+#undef LXV
+
#define STVE(name, access, swap, element) \
void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
target_ulong addr) \
diff --git a/target-ppc/translate/vsx-impl.inc.c
b/target-ppc/translate/vsx-impl.inc.c
index fb29e6d..0c3a0dd 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -102,6 +102,26 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(tmp);
}
+#define VSX_LOAD_VECTOR(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, EA); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ gen_helper_##name(cpu_vsrl(xT(ctx->opcode)), cpu_env, EA); \
+ tcg_temp_free(EA); \
+}
+
+VSX_LOAD_VECTOR(lxvb16x)
+VSX_LOAD_VECTOR(lxvh8x)
+
#define VSX_STORE_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target-ppc/translate/vsx-ops.inc.c
b/target-ppc/translate/vsx-ops.inc.c
index 414b73b..598b349 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -7,6 +7,8 @@ GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE,
PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.7.4
