Hi,
Your series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v3 00/34] cmpxchg-based emulation of atomics
Type: series
Message-id: 1472935202-3342-1-git-send-email-...@twiddle.net
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1472935202-3342-1-git-send-email-...@twiddle.net
-> patchew/1472935202-3342-1-git-send-email-...@twiddle.net
Switched to a new branch 'test'
7d6f99f target-alpha: Emulate LL/SC using cmpxchg helpers
95c65de target-alpha: Introduce MMU_PHYS_IDX
0250b51 target-arm: remove EXCP_STREX + cpu_exclusive_{test, info}
f5fb6dc linux-user: remove handling of aarch64's EXCP_STREX
5205e25 linux-user: remove handling of ARM's EXCP_STREX
779b958 target-arm: emulate aarch64's LL/SC using cmpxchg helpers
e78b7c8 target-arm: emulate SWP with atomic_xchg helper
0d71586 target-arm: emulate LL/SC using cmpxchg helpers
f3c834e target-arm: Rearrange aa32 load and store functions
9caae16 tests: add atomic_add-bench
01cb92d target-i386: remove helper_lock()
3b0638f target-i386: emulate XCHG using atomic helper
299454c target-i386: emulate LOCK'ed BTX ops using atomic helpers
ea9bf7b target-i386: emulate LOCK'ed XADD using atomic helper
9ed94c7 target-i386: emulate LOCK'ed NEG using cmpxchg helper
b114db2 target-i386: emulate LOCK'ed NOT using atomic helper
98ed70e target-i386: emulate LOCK'ed INC using atomic helper
6864197 target-i386: emulate LOCK'ed OP instructions using atomic helpers
60ea4a3 target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers
49c8f18 tcg: Add CONFIG_ATOMIC64
924cf07 tcg: Add atomic128 helpers
6f824c0 tcg: Add atomic helpers
289ae34 cputlb: Tidy some macros
6688a03 cputlb: Move most of iotlb code out of line
1233d51 cputlb: Remove includes from softmmu_template.h
ef3611f cputlb: Move probe_write out of softmmu_template.h
c2fe267 cputlb: Replace SHIFT with DATA_SIZE
be5d2eb HACK: Always enable parallel_cpus
5abdfaa tcg: Add EXCP_ATOMIC
45280a3 int128: Add int128_make128
fefab1d int128: Use __int128 if available
b302da3 exec: Avoid direct references to Int128 parts
b2eec15 atomics: add atomic_op_fetch variants
78a61f7 atomics: add atomic_xor
=== OUTPUT BEGIN ===
Checking PATCH 1/34: atomics: add atomic_xor...
Checking PATCH 2/34: atomics: add atomic_op_fetch variants...
Checking PATCH 3/34: exec: Avoid direct references to Int128 parts...
Checking PATCH 4/34: int128: Use __int128 if available...
Checking PATCH 5/34: int128: Add int128_make128...
Checking PATCH 6/34: tcg: Add EXCP_ATOMIC...
Checking PATCH 7/34: HACK: Always enable parallel_cpus...
Checking PATCH 8/34: cputlb: Replace SHIFT with DATA_SIZE...
Checking PATCH 9/34: cputlb: Move probe_write out of softmmu_template.h...
Checking PATCH 10/34: cputlb: Remove includes from softmmu_template.h...
Checking PATCH 11/34: cputlb: Move most of iotlb code out of line...
Checking PATCH 12/34: cputlb: Tidy some macros...
Checking PATCH 13/34: tcg: Add atomic helpers...
Checking PATCH 14/34: tcg: Add atomic128 helpers...
Checking PATCH 15/34: tcg: Add CONFIG_ATOMIC64...
ERROR: Macros with complex values should be enclosed in parenthesis
#128: FILE: tcg/tcg-op.c:2027:
+# define WITH_ATOMIC64(X) X,
total: 1 errors, 0 warnings, 262 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/34: target-i386: emulate LOCK'ed cmpxchg using cmpxchg
helpers...
Checking PATCH 17/34: target-i386: emulate LOCK'ed OP instructions using atomic
helpers...
Checking PATCH 18/34: target-i386: emulate LOCK'ed INC using atomic helper...
Checking PATCH 19/34: target-i386: emulate LOCK'ed NOT using atomic helper...
Checking PATCH 20/34: target-i386: emulate LOCK'ed NEG using cmpxchg helper...
Checking PATCH 21/34: target-i386: emulate LOCK'ed XADD using atomic helper...
Checking PATCH 22/34: target-i386: emulate LOCK'ed BTX ops using atomic
helpers...
Checking PATCH 23/34: target-i386: emulate XCHG using atomic helper...
Checking PATCH 24/34: target-i386: remove helper_lock()...
Checking PATCH 25/34: tests: add atomic_add-bench...
Checking PATCH 26/34: target-arm: Rearrange aa32 load and store functions...
Checking PATCH 27/34: target-arm: emulate LL/SC using cmpxchg helpers...
Checking PATCH 28/34: target-arm: emulate SWP with atomic_xchg helper...
Checking PATCH 29/34: target-arm: emulate aarch64's LL/SC using cmpxchg
helpers...
Checking PATCH 30/34: linux-user: remove handling of ARM's EXCP_STREX...
Checking PATCH 31/34: linux-user: remove handling of aarch64's EXCP_STREX...
Checking PATCH 32/34: target-arm: remove EXCP_STREX + cpu_exclusive_{test,
info}...
Checking PATCH 33/34: target-alpha: Introduce MMU_PHYS_IDX...
Checking PATCH 34/34: target-alpha: Emulate LL/SC using cmpxchg helpers...
=== OUTPUT END ===
Test command exited with code: 1
---
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