This series contains 4 new instructions for POWER9 ISA3.0
Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.
Patches:
01: darn: Deliver a random number
02: lxvw4x - improve implementation
03: stxv4x - improve implementation
04: lxvh8x: Load VSX Vector Halfword*8
stxvh8x: Store VSX Vector Halfword*8
05: lxvb16x: Load VSX Vector Byte*16
stxvb16x: Store VSX Vector Byte*16
Changelog:
v2:
* Fix lxvw4x/stxv4x translation as LE/BE were both similar
one in tcg and other as helper
* Rename bswap32x2 to deposit32x2 as it does not need to
swap content(32bit)
* stxvh8x had a bug as David suggested.
v1:
* More load/store cleanups in byte reverse routines
* ld64/st64 converted to newer macro and updated call sites
* Cleanup load with reservation and store conditional
* Return invalid random for darn instruction
v0:
* darn - read /dev/random to get the random number
* xxspltib - make is PPC64 only
* Consolidate load/store operations and use macros to generate qemu_st/ld
* Simplify load/store vsx endian manipulation
Nikunj A Dadhania (4):
target-ppc: improve lxvw4x implementation
target-ppc: improve stxvw4x implementation
target-ppc: add lxvh8x and stxvh8x
target-ppc: add lxvb16x and stxvb16x
Ravi Bangoria (1):
target-ppc: implement darn instruction
target-ppc/helper.h | 4 +
target-ppc/int_helper.c | 16 ++++
target-ppc/mem_helper.c | 11 +++
target-ppc/translate.c | 18 +++++
target-ppc/translate/vsx-impl.inc.c | 146 ++++++++++++++++++++++++++++++------
target-ppc/translate/vsx-ops.inc.c | 4 +
6 files changed, 175 insertions(+), 24 deletions(-)
--
2.7.4
