If tagged addresses are enabled, then addresses being loaded into the 
    PC must be cleaned up by overwriting the tag bits with either all 0's 
    or all 1's as specified in the ARM ARM spec.  The decision process is 
    dependent on whether the code will be running in EL0/1 or in EL2/3 and 
    is controlled by a combination of Top Byte Ignored (TBI) bits in the 
    TCR and the value of bit 55 in the address being loaded. 
    TBI values are extracted from the appropriate TCR and made available 
    to TCG code generation routines by inserting them into the TB flags 
    field and then transferring them to DisasContext structure in 

    New function gen_a64_set_pc_reg() encapsulates the logic required to 
    determine whether clean up of the tag byte is required and then 
    generating the code to correctly load the PC.
    In addition to those instruction which can directly load a tagged 
    address into the PC, there are others which increment or add a value to
    the PC.  If 56 bit addressing is used, these instructions can cause an 
    arithmetic roll-over into the tag bits.  The ARM ARM specification for 
    handling tagged addresses requires that these cases also be addressed
    by cleaning up the tag field.  This work has been deferred because 
    there is currently no CPU model available for testing with 56 bit 

Thomas Hanson (3):
  target-arm: Infrastucture changes to enable handling of tagged address
    loading into PC
  target-arm: Code changes to implement overwrite of tag field on PC
  target-arm: Comments to mark location of pending work for 56 bit

 target-arm/cpu.h           | 20 +++++++++--
 target-arm/helper.c        | 42 +++++++++++++++++++++++
 target-arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++-----
 target-arm/translate.h     |  3 ++
 4 files changed, 140 insertions(+), 10 deletions(-)


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