Hi Paolo,
> -----Original Message-----
> From: Wu, Feng
> Sent: Thursday, September 22, 2016 12:12 AM
> To: qemu-devel@nongnu.org
> Cc: pbonz...@redhat.com; Wu, Feng <feng...@intel.com>
> Subject: [PATCH] intel-iommu: Check IOAPIC's Trigger Mode against the one in
> IRTE
>
> The Trigger Mode field of IOAPIC must match the Trigger Mode in
> the IRTE according to VT-d Spec 5.1.5.1.
Any comments about this patch? Thanks a lot!
Thanks,
Feng
>
> Signed-off-by: Feng Wu <feng...@intel.com>
> ---
> hw/i386/intel_iommu.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 28c31a2..f32ad5c 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -27,6 +27,7 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/i386/pc.h"
> +#include "hw/i386/apic-msidef.h"
> #include "hw/boards.h"
> #include "hw/i386/x86-iommu.h"
> #include "hw/pci-host/q35.h"
> @@ -2203,6 +2204,8 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState
> *iommu,
> }
> } else {
> uint8_t vector = origin->data & 0xff;
> + uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) &
> 0x1;
> +
> VTD_DPRINTF(IR, "received IOAPIC interrupt");
> /* IOAPIC entry vector should be aligned with IRTE vector
> * (see vt-d spec 5.1.5.1). */
> @@ -2211,6 +2214,15 @@ static int
> vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
> "entry: %d, IRTE: %d, index: %d",
> vector, irq.vector, index);
> }
> +
> + /* The Trigger Mode field must match the Trigger Mode in the IRTE.
> + * (see vt-d spec 5.1.5.1). */
> + if (trigger_mode != irq.trigger_mode) {
> + VTD_DPRINTF(GENERAL, "IOAPIC trigger mode inconsistent: "
> + "entry: %u, IRTE: %u, index: %d",
> + trigger_mode, irq.trigger_mode, index);
> + }
> +
> }
>
> /*
> --
> 1.9.1
