On 30.09.2016 12:19, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Fix the decoding of iss_sf in disas_ld_lit.
> The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
> is a bit that specifies the width of the register that the
> instruction loads to.
>
> If cleared it specifies 32 bits.
> If set it specifies 64 bits.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> target-arm/translate-a64.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index ddf52f5..eae25c3 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -2025,7 +2025,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
> do_fp_ld(s, rt, tcg_addr, size);
> } else {
> /* Only unsigned 32bit loads target 32bit registers. */
> - bool iss_sf = opc == 0 ? 32 : 64;
> + bool iss_sf = opc == 0 ? false : true;
You could simplify that to:
bool iss_sf = !(opc == 0);
Thomas
