If tagged addresses are enabled, then addresses being loaded into the PC must be cleaned up by overwriting the tag bits with either all 0's or all 1's as specified in the ARM ARM spec. The decision process is dependent on whether the code will be running in EL0/1 or in EL2/3 and is controlled by a combination of Top Byte Ignored (TBI) bits in the TCR and the value of bit 55 in the address being loaded. TBI values are extracted from the appropriate TCR and made available to TCG code generation routines by inserting them into the TB flags field and then transferring them to DisasContext structure in gen_intermediate_code_a64().
New function gen_a64_set_pc_var() encapsulates the logic required to determine whether clean up of the tag byte is required and then generating the code to correctly load the PC. New function gen_a64_set_pc_reg() accepts a register number and then calls gen_a64_set_pc_var(). In addition to those instruction which can directly load a tagged address into the PC, there are others which increment or add a value to the PC. If 56 bit addressing is used, these instructions can cause an arithmetic roll-over into the tag bits. The ARM ARM specification for handling tagged addresses requires that these cases also be addressed by cleaning up the tag field. This work has been deferred because there is currently no CPU model available for testing with 56 bit addresses. v1->v2: - Updated patch descriptions per Peter's commments - Added function header and other comments as recommended - Change return type from long to unit32_t for arm_regime_tbi0() & arm_regime_tbi1() - Moved prototype of gen_a64_set_pc_reg() from patch 1 to patch 2 - Moved assignment of dc->tbi0 & dc->tbi1 from patch 2 to patch 1 - Split out documentation comments into separate patch. v2->v3 - Split gen_a64_set_pc_reg() into 2 functions: * gen_a64_set_pc_var() which takes a TCGv_i64 argument and * gen_a64_set_pc_reg() which takes a register number and calls gen_a64_set_pc_var() after mapping the register to a variable Still looking into handling of tagged addresses for exceptions and exception returns. Will handle that as a separate patch set. Thomas Hanson (4): target-arm: Infrastucture changes to enable handling of tagged address loading into PC target-arm: Code changes to implement overwrite of tag field on PC load target-arm: Comments to mark location of pending work for 56 bit addresses target-arm: Comments added to identify cases in a switch