On 10/13/2016 04:52 AM, David Gibson wrote:
> On Mon, Oct 03, 2016 at 09:24:44AM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt <b...@kernel.crashing.org>
>> The LPC (Low Pin Count) interface on a POWER8 is made accessible to
>> the system through the ADU (XSCOM interface). This interface is part
>> of set of units connected together via a local OPB (On-Chip Peripheral
>> Bus) which act as a bridge between the ADU and the off chip LPC
>> endpoints, like external flash modules.
>> The most important units of this OPB are :
>>  - OPB Master: contains the ADU slave logic, a set of internal
>>    registers and the logic to control the OPB.
>>  - LPCHC (LPC HOST Controller): which implements a OPB Slave, a set of
>>    internal registers and the LPC HOST Controller to control the LPC
>>    interface.
>> Four address spaces are provided to the ADU :
>>  - LPC Bus Firmware Memory
>>  - LPC Bus Memory
>>  - LPC Bus I/O (ISA bus)
>>  - and the registers for the OPB Master and the LPC Host Controller
>> On POWER8, an intermediate hop is necessary to reach the OPB, through
>> a unit called the ECCB. OPB commands are simply mangled in ECCB write
>> commands.
>> On POWER9, the OPB master address space can be accessed via MMIO. The
>> logic is same but the code will be simpler as the XSCOM and ECCB hops
>> are not necessary anymore.
>> This version of the LPC controller model doesn't yet implement support
>> for the SerIRQ deserializer present in the Naples version of the chip
>> though some preliminary work is there.
>> Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org>
>> [clg: - updated for qemu-2.7
>>       - ported on latest PowerNV patchset
>>       - changed the XSCOM interface to fit new model
>>       - QOMified the model
>>       - moved the ISA hunks in another patch
>>       - removed printf logging
>>       - added a couple of UNIMP logging
>>       - rewrote commit log ]
>> Signed-off-by: Cédric Le Goater <c...@kaod.org>
> It looks reasonable as far as it goes.
> I don't see anything wiring this up to qemu's common ISA
> infrastructure, which seems a bit odd.

Yes. I wanted to distinguish the wiring from the model. It is because
there is two different ways to handle the interrupt depending on the
chip type and also because we pick chip[0]->lpc to be the primary bus.



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