> On Mon, Oct 10, 2016 at 15:59:02 +0200, Paolo Bonzini wrote:
> > See each patch. My attempt at fixing whatever I did when I obviously
> > didn't know enough^W about the C11 memory model, and at setting a
> > better example for future generations...
> Just for context. Building on this patchset, is it now time to
> phase out smp_(rw)mb in favour or C11's acq/rel, as you laid
> out in your KVM Forum talk [*]?
Yes, this would be the start of it. However I'm a bit undecided
because ARMv8 doesn't have acq/rel memory barriers, and its STLR
opcode is stronger than a store release.
> What is the plan with smp_mb_(sg)et? It's not clear to me from
> the slides, but given patch 5 I don't see a reason to keep them.
No plan for now. It makes sense to phase out at least atomic_mb_read.
atomic_mb_set is more efficient on x86 than store+mfence, so there's