On Mon, Oct 03, 2016 at 09:24:54AM +0200, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > The OCC is an on-chip microcontroller based on a ppc405 core used > for various power management tasks. It comes with a pile of additional > hardware sitting on the PIB (aka XSCOM bus). At this point we don't > emulate it (nor plan to do so). However there is one facility which > is provided by the surrounding hardware that we do need, which is the > interrupt generation facility. OPAL uses it to send itself interrupts > under some circumstances and there are other uses around the corner. > > So this implement just enough to support this. > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > [clg: - updated for qemu-2.7 > - changed the XSCOM interface to fit new model > - QOMified the model ] > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>
> ---
> hw/ppc/Makefile.objs | 2 +-
> hw/ppc/pnv.c | 11 ++++
> hw/ppc/pnv_occ.c | 135
> +++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/pnv.h | 2 +
> include/hw/ppc/pnv_occ.h | 38 +++++++++++++
> include/hw/ppc/pnv_xscom.h | 3 +
> 6 files changed, 190 insertions(+), 1 deletion(-)
> create mode 100644 hw/ppc/pnv_occ.c
> create mode 100644 include/hw/ppc/pnv_occ.h
>
> diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
> index 4feb15b360c8..35b11cf887d5 100644
> --- a/hw/ppc/Makefile.objs
> +++ b/hw/ppc/Makefile.objs
> @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) += spapr_hcall.o spapr_iommu.o
> spapr_rtas.o
> obj-$(CONFIG_PSERIES) += spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng.o
> obj-$(CONFIG_PSERIES) += spapr_cpu_core.o
> # IBM PowerNV
> -obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o
> +obj-$(CONFIG_POWERNV) += pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_psi.o
> pnv_occ.o
> ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy)
> obj-y += spapr_pci_vfio.o
> endif
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b17e205c74db..e805e97d4d87 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -651,6 +651,11 @@ static void pnv_chip_init(Object *obj)
>
> object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
> object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
> +
> + object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
> + object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
> + object_property_add_const_link(OBJECT(&chip->occ), "psi",
> + OBJECT(&chip->psi), &error_abort);
> }
>
> static void pnv_chip_realize(DeviceState *dev, Error **errp)
> @@ -740,6 +745,12 @@ static void pnv_chip_realize(DeviceState *dev, Error
> **errp)
> &error_fatal);
> memory_region_add_subregion(&chip->xscom, PNV_XSCOM_LPC_BASE << 3,
> &chip->lpc.xscom_regs);
> +
> + /* Create the simplified OCC model */
> + object_property_set_bool(OBJECT(&chip->occ), true, "realized",
> + &error_fatal);
> + memory_region_add_subregion(&chip->xscom, PNV_XSCOM_OCC_BASE << 3,
> + &chip->occ.xscom_regs);
> }
>
> static Property pnv_chip_properties[] = {
> diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
> new file mode 100644
> index 000000000000..250517cca0ef
> --- /dev/null
> +++ b/hw/ppc/pnv_occ.c
> @@ -0,0 +1,135 @@
> +/*
> + * QEMU PowerNV Emulation of a few OCC related registers
> + *
> + * Copyright (c) 2016, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/hw.h"
> +#include "sysemu/sysemu.h"
> +#include "target-ppc/cpu.h"
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_occ.h"
> +
> +#define OCB_OCI_OCCMISC 0x4020
> +#define OCB_OCI_OCCMISC_AND 0x4021
> +#define OCB_OCI_OCCMISC_OR 0x4022
> +
> +static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
> +{
> + bool irq_state;
> +
> + val &= 0xffff000000000000ull;
> +
> + occ->occmisc = val;
> + irq_state = !!(val >> 63);
> + pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
> +}
> +
> +static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + PnvOCC *occ = PNV_OCC(opaque);
> + uint32_t offset = addr >> 3;
> + uint64_t val = 0;
> +
> + switch (offset) {
> + case OCB_OCI_OCCMISC:
> + val = occ->occmisc;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> + HWADDR_PRIx "\n", addr);
> + }
> + return val;
> +}
> +
> +static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvOCC *occ = PNV_OCC(opaque);
> + uint32_t offset = addr >> 3;
> +
> + switch (offset) {
> + case OCB_OCI_OCCMISC_AND:
> + pnv_occ_set_misc(occ, occ->occmisc & val);
> + break;
> + case OCB_OCI_OCCMISC_OR:
> + pnv_occ_set_misc(occ, occ->occmisc | val);
> + break;
> + case OCB_OCI_OCCMISC:
> + pnv_occ_set_misc(occ, val);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
> + HWADDR_PRIx "\n", addr);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_occ_xscom_ops = {
> + .read = pnv_occ_xscom_read,
> + .write = pnv_occ_xscom_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +
> +static void pnv_occ_realize(DeviceState *dev, Error **errp)
> +{
> + PnvOCC *occ = PNV_OCC(dev);
> + Object *obj;
> + Error *error = NULL;
> +
> + occ->occmisc = 0;
> +
> + /* get PSI object from chip */
> + obj = object_property_get_link(OBJECT(dev), "psi", &error);
> + if (!obj) {
> + error_setg(errp, "%s: required link 'psi' not found: %s",
> + __func__, error_get_pretty(error));
> + return;
> + }
> + occ->psi = PNV_PSI(obj);
> +
> + /* XScom region for OCC registers */
> + memory_region_init_io(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
> + occ, "xscom-occ", PNV_XSCOM_OCC_SIZE << 3);
> +}
> +
> +static void pnv_occ_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = pnv_occ_realize;
> +}
> +
> +static const TypeInfo pnv_occ_type_info = {
> + .name = TYPE_PNV_OCC,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvOCC),
> + .class_init = pnv_occ_class_init,
> +};
> +
> +static void pnv_occ_register_types(void)
> +{
> + type_register_static(&pnv_occ_type_info);
> +}
> +
> +type_init(pnv_occ_register_types)
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 473fd2318d87..ed3316501326 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -25,6 +25,7 @@
> #include "hw/ppc/pnv_lpc.h"
> #include "hw/ppc/xics.h"
> #include "hw/ppc/pnv_psi.h"
> +#include "hw/ppc/pnv_occ.h"
>
> #define TYPE_PNV_CHIP "powernv-chip"
> #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
> @@ -59,6 +60,7 @@ typedef struct PnvChip {
> PnvLpcController lpc;
> XICSNative xics;
> PnvPsiController psi;
> + PnvOCC occ;
> } PnvChip;
>
> typedef struct PnvChipClass {
> diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
> new file mode 100644
> index 000000000000..54e760df7c4f
> --- /dev/null
> +++ b/include/hw/ppc/pnv_occ.h
> @@ -0,0 +1,38 @@
> +/*
> + * QEMU PowerNV Emulation of a few OCC related registers
> + *
> + * Copyright (c) 2016, IBM Corporation.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> <http://www.gnu.org/licenses/>.
> + */
> +#ifndef _PPC_PNV_OCC_H
> +#define _PPC_PNV_OCC_H
> +
> +#define TYPE_PNV_OCC "pnv-occ"
> +#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC)
> +
> +typedef struct PnvPsiController PnvPsiController;
> +
> +typedef struct PnvOCC {
> + DeviceState xd;
> +
> + /* OCC Misc interrupt */
> + uint64_t occmisc;
> +
> + PnvPsiController *psi;
> +
> + MemoryRegion xscom_regs;
> +} PnvOCC;
> +
> +#endif /* _PPC_PNV_OCC_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index 28fbec8ee8e0..f22906dc2fff 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -66,6 +66,9 @@ typedef struct PnvXScomInterfaceClass {
> #define PNV_XSCOM_PSI_BASE 0x2010900
> #define PNV_XSCOM_PSI_SIZE 0x20
>
> +#define PNV_XSCOM_OCC_BASE 0x0066000
> +#define PNV_XSCOM_OCC_SIZE 0x6000
> +
> extern void pnv_xscom_realize(PnvChip *chip, Error **errp);
> extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset);
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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