+-- On Wed, 26 Oct 2016, Alistair Francis wrote --+ | > * Device model for Cadence UART | > + * -> http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf | | Nit pick, I would put the URL under the title below.
Okay. | > + case R_BRGR: /* Baud rate generator */ | > + s->r[offset] = 0x028B; /* default reset value */ | | Why do we still have the reset value here, I thought we were just | ignoring the invalid writes? You don't need to reset it. Wouldn't that leave the registers undefined ? Thank you. -- Prasad J Pandit / Red Hat Product Security Team 47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
