On 11/03/2016 11:52 AM, Paolo Bonzini wrote:
UP kernel = no sane way to implement this in user-mode qemu?
Probably no straight-forward way, no.
Another possibility is to treat the load as a LL and the store as a SC (implemented in turn with cmpxchg+branch if it fails). cmpxchg spans two basic blocks, so maybe one also needs to look at r0 and sp in cpu_get_tb_cpu_state...
Yeah, that's a possibility. With the store-conditional failure auto-branching back to the start of the sequence (r0+sp).
Anyhow this patch seems like a bugfix.
Absolutely. r~
