On 11/29/2016 04:44 PM, Cédric Le Goater wrote: > From: Joel Stanley <[email protected]> > > The Aspeed SoC includes a set of watchdog timers using 32-bit > decrement counters, which can be based either on the APB clock or > a 1 MHz clock. > > The watchdog timer is designed to prevent system deadlock and, in > general, it should be restarted before timeout. When a timeout occurs, > different types of signals can be generated, ARM reset, SOC reset, > System reset, CPU Interrupt, external signal or boot from alternate > block. The current model only performs the system reset function as > this is used by U-Boot and Linux. >
Shall I resend the 3/4 patches related to the watchdog in a separate patchset ? Thanks, C.
